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| note: this is a summary document. the complete document is available on the atmel website at www.atmel.com. features ? high performance, low power 32-bit avr ? microcontroller ? compact single-cycle risc instruction set including dsp instruction set ? built-in floating-point processing unit (fpu) ? read-modify-write instructions and atomic bit manipulation ? performing 1.49 dmips / mhz ? up to 91 dmips running at 66 mhz from flash (1 wait-state) ? up to 49 dmips running at 33 mhz from flash (0 wait-state) ? memory protection unit ? multi-hierarchy bus system ? high-performance data transfers on separate buses for increased performance ? 16 peripheral dma channels improves speed for peripheral communication ? internal high-speed flash ? 512 kbytes, 256 kbytes, 128 kbytes, 64 kbytes versions ? single cycle access up to 33 mhz ?flashvault ? technology allows pre-programmed secure library support for end user applications ? prefetch buffer optimizing instru ction execution at maximum speed ? 100,000 write cycles, 15-year data retention capability ? flash security locks and us er defined configuration area ? internal high-speed sram, si ngle-cycle access at full speed ? 64 kbytes (512 kb and 256 kb flash), 32 kb ytes (128 kb flash), 16 kbytes (64 kb flash) ? 4 kbytes on the multi-layer bus system (hsb ram) ? external memory interface on at32uc3c0 derivatives ? sdram / sram compatible memory bus (16-bit data and 24-bit address buses) ? interrupt controller ? autovectored low latency interrupt service with programmable priority ? system functions ? power and clock manager ? internal 115khz (rcsys) and 8m hz/1mhz (rc8m) rc oscillators ? one 32 khz and two multipurpose oscillators ? clock failure detection ? two phase-lock-loop (pll) allowing independent cpu frequency from usb or can frequency ? windowed watchdog timer (wdt) ? asynchronous timer (ast) with real-tim e clock capability ? counter or calendar mode supported ? frequency meter (freqm) for accurate measuring of clock frequency ? ethernet mac 10/100 mbps interface ? 802.3 ethernet me dia access controller ? supports media independent interf ace (mii) and reduced mii (rmii) ? universal serial bus (usb) ? device 2.0 and embedded host low speed and full speed ? flexible end-point configuration and management with dedicated dma channels ? on-chip transceivers including pull-ups ? one 2-channel controller area network (can) ? can2a and can2b protocol complian t, with high-level mailbox system ? two independent channels, 16 message objects per channel 32117ds?avr?01/12 32-bit avr ? microcontroller at32uc3c0512c at32uc3c0256c at32uc3c0128c at32uc3c064c at32uc3c1512c at32uc3c1256c AT32UC3C1128C at32uc3c164c at32uc3c2512c at32uc3c2256c at32uc3c2128c at32uc3c264c summary
2 32117ds?avr-01/12 at32uc3c ? one 4-channel 20-bit pulse width modulation controller (pwm) ? complementary outputs, wi th dead time insertion ? output override and fault protection ? two quadrature decoders ? one 16-channel 12-bit pi pelined analog-to-digital converter (adc) ? dual sample and hold capability allowing 2 synchronous conversions ? single-ended and differential channels, window function ? two 12-bit digital-to-analog converters (dac), with dual ou tput sample system ? four analog comparators ? six 16-bit timer/co unter (tc) channels ? external clock inputs, pwm, capture and various counting capabilities ? one peripheral event controller ? trigger actions in peripherals de pending on events generated from peripherals or from input pins ? deterministic trigger ? 34 events and 22 event actions ? five universal synchronous/asynchro nous receiver/transmitters (usart) ? independent baudrate generator, support for spi, lin, irda and iso7816 interfaces ? support for hardware handshakin g, rs485 interfaces and modem line ? two master/slave serial peripheral interfaces (spi) with chip select signals ? one inter-ic sound (i2s) controller ? compliant with i2s bus specification ? time division multiplexed mode ? three master and three slave two-wi re interfaces (twi), 400kbit/s i 2 c-compatible ? qtouch ? library support ? capacitive touch buttons, sliders, and wheels ?qtouch ? and qmatrix ? acquisition ? on-chip non-intrusive debug system ? nexus class 2+, runtime control, non-intrusive data and program trace ?awire ? single-pin programming trace and de bug interface muxed with reset pin ? nanotrace ? provides trace capabilities through jtag or awire interface ? 3 package options ? 64-pin qfn/tqfp (45 gpio pins) ? 100-pin tqfp (81 gpio pins) ? 144-pin lqfp (123 gpio pins) ? two operating voltage ranges: ? single 5v power supply ? single 3.3v power supply 3 32117ds?avr-01/12 at32uc3c 1. description the at32uc3c is a complete system-on-chip microcontroller based on the avr32uc risc processor running at frequencies up to 66 mhz. avr32uc is a high-performance 32-bit risc microprocessor core, designed for cost-sensitive embedded applications, with particular empha- sis on low power consumption, high code density and high performance. the processor implements a memory protection unit (mpu) and a fast and flexible interrupt con- troller for supporting modern operating systems and real-time operating systems. using the secure access unit (sau) together with the mpu provides the required security and integrity. higher computation capabilities ar e achievable either using a ri ch set of dsp instructions or using the floating-point instructions. the at32uc3c incorporates on-chip flash and sram memories for secure and fast access. for applications requiring additional memory, an external memory interface is provided on at32uc3c0 derivatives. the memory direct memory access controller (mdma) enables transfers of block of data from memories to memories without processor involvement. the peripheral direct memory access (pdca) controller enables data transfers between periph- erals and memories without processor involvement. the pdca drastically reduces processing overhead when transferring continuous and large data streams. the at32uc3c incorporates on-chip flash and sram memories for secure and fast access. the flashvault technology allows secure libraries to be programmed into the device. the secure libraries can be executed while the cpu is in secure state, but not read by non-secure software in the device. the device can thus be shipped to end custumers, who are able to program their own code into the device, accessing the secure libraries, without any risk of compromising the proprietary secure code. the power manager improves design flexibility and security. power monitoring is supported by on-chip power-on reset (por), brown-out detectors (bod18, bod33, bod50). the cpu runs from the on-chip rc oscillators, the plls, or the multipurpose oscillators. the asynchro- nous timer (ast) combined with the 32 khz osci llator keeps track of the time. the ast can operate in counter or calendar mode. the device includes six identical 16-bit timer/counter (tc) channels. each channel can be inde- pendently programmed to perform frequency measurement, event counting, interval measurement, pulse generation, delay timing, and pulse width modulation. the pwm module provides four channels with m any configuration options including polarity, edge alignment and waveform non overlap control. the pwm channels can operate indepen- dently, with duty cycles set independently from each other, or in interlinked mode, with multiple channels updated at the same time. it also includes safety feature with fault inputs and the ability to lock the pwm configuration registers and the pwm pin assignment. the at32uc3c also features many communication interfaces for communication intensive applications. in addition to standard serial interfaces like uart, spi or twi, other interfaces like flexible can, usb and ethernet mac are available. the usart supports different communica- tion modes, like spi mode and lin mode. the inter-ic sound controller (i2sc) provides a 5-bit wide, bidirectional, synchronous, digital audio link with off-chip audio devices. the controlle r is compliant with the i2s bus specification. 4 32117ds?avr-01/12 at32uc3c the full-speed usb 2.0 device interface supports several usb classes at the same time thanks to the rich end-point configuration. t he on-the-go (otg) host interface allows device like a usb flash disk or a usb printer to be directly connected to the processor. the media-independent interface (mii) and reduced mii (rmii) 10/100 ethernet mac module provides on-chip solutions for network-connected devices. the peripheral event controller (pevc) allows to redirect events from one peripheral or from input pins to another peripheral. it can then trigger, in a deterministic time, an action inside a peripheral without the need of cpu. for instanc e a pwm waveform can directly trigger an adc capture, hence avoiding delays due to software interrupt processing. the at32uc3c features analog functions like adc, dac, analog comparators. the adc inter- face is built around a 12-bit pipelined adc core and is able to control two independent 8-channel or one 16-channel. the adc block is able to measure two different voltages sampled at the same time. the analog comparators can be pair ed to detect when the sensing voltage is within or outside the defined reference window. atmel offers the qtouch library for embedding capacitive touch buttons, sliders, and wheels functionality into avr microcontrollers. the patented charge-transfer signal acquisition offers robust sensing and included fully debounced reporting of touch keys and includes adjacent key suppression ? (aks ? ) technology for unambiguous detection of key events. the easy-to-use qtouch suite toolchain allows you to explore, develop, and debug your own touch applications. at32uc3c integrates a class 2+ nexus 2.0 on-chip debug (ocd) system, with non-intrusive real-time trace, full-speed read/write memory access in addition to basic runtime control. the nanotrace interface enables trace feature for awire- or jtag-based debuggers. the single-pin awire interface allows all features available th rough the jtag interface to be accessed through the reset pin, allowing th e jtag pins to be used for gpio or peripherals. 5 32117ds?avr-01/12 at32uc3c 2. overview 2.1 block diagram figure 2-1. block diagram supplied by vddana supplied by vddana peripheral dma controller hsb-pb bridge b hsb-pb bridge a general purpose ios general purpose ios pa pb pc pd pa pb pc pd usb interface id vbof vbus d- d+ canif 32 khz osc rcsys osc0 / osc1 pll0 / pll1 jtag interface mcko mdo[5..0] mseo[1..0] evti_n evto_n tdi rxline[0] pb pb hsb hsb txline[0] rxline[1] txcan[1] peripheral event controller pad_evt mm m s s m high speed bus matrix avr32uc cpu nexus class 2+ ocd instr interface data interface memory interface 64/32/16 kb sram memory protection unit local bus interface m 4 kb hsb ram s s external bus interface (sdram & static memory controller) cas ras sda10 sdck sdcke sdwe ncs[3..0] nrd nwait nwe0 data[15..0] addr[23..0] nwe1 memory dma hsb-pb bridge c pb hsb s m s m configuration registers bus pbb serial peripheral interface 1 dma miso, mosi npcs[3..0] sck usart0 usart2 usart3 dma rxd txd clk rts, cts twck twd two-wire interface 0/1 dma pulse width modulation controller dma digital to analog converter 0/1 dma dac0a/b analog comparator 0a/0b/1a/1b ac0ap/n ac0bp/n ac1ap/n ac1bp/n dac1a/b i2s interface dma timer/counter 1 a[2..0] b[2..0] clk[2..0] quadrature decoder 0/1 qepa qepb qepi xin32 xout32 xin[1:0] xout[1:0] timer/counter 0 clk[2..0] a[2..0] b[2..0] analog to digital converter 0/1 dma adcin[15..0] adcvrefp/n usart1 dma rxd txd clk rts, cts dsr, dtr, dcd, ri pbc pba serial peripheral interface 0 dma sck miso, mosi npcs[3..0] m r w pwml[3..0] pwmh[3..0] adcref0/1 awire reset_n asynchronous timer watchdog timer frequency meter power manager reset controller sleep controller clock controller system control interface gclk[1..0] bods (1.8v, 3.3v, 5v) rc8m ac0aout/ac0bout ac1aout/ac1bout external interrupt controller extint[8:1] nmi two-wire interface 2 dma twd twck ethernet mac dma s col, crs, rxd[3..0], rx_clk, rx_dv, rx_er, tx_clk mdc, txd[3..0], tx_en, tx_er, speed mdio m 512/ 256/ 128/64 kb flash flash controller bclk iws isdo mclk l o c a l b u s dacref isdi tms tck tdo rc120m ext_faults[1:0] twalm usart4 dma rxd txd clk rts, cts 6 32117ds?avr-01/12 at32uc3c 2.2 configuration summary table 2-1. configuration summary feature at32uc3c0512c/ at32uc3c0256c/ at32uc3c0128c/ at32uc3c064c at32uc3c1512c/ at32uc3c1256c/ AT32UC3C1128C/ at32uc3c164c at32uc3c2512c/ at32uc3c2256c/ at32uc3c2128c/ at32uc3c264c flash 512/256/128/64 kb 512/256/ 128/64 kb 512/256/128/64 kb sram 64/64/32/16kb 64/ 64/32/16kb 64/64/32/16kb hsb ram 4 kb ebi 1 0 0 gpio 123 81 45 external interrupts 8 8 8 twi 3 3 2 usart 5 5 4 peripheral dma channels 16 16 16 peripheral event system 1 1 1 spi 2 2 1 can channels 2 2 2 usb 1 1 1 ethernet mac 10/100 1 rmii/mii 1 rmii/mii 1 rmii only i2s 1 1 1 asynchronous timers 1 1 1 timer/counter channels 6 6 3 pwm channels 4x2 qdec 2 2 1 frequency meter 1 watchdog timer 1 power manager 1 oscillators pll 80-240 mhz (pll0/pll1) crystal oscillator 0.4-20 mhz (osc0) crystal oscillator 32 khz (osc32k) rc oscillator 115 khz (rcsys) rc oscillator 8 mhz (rc8m) rc oscillator 120 mhz (rc120m) 0.4-20 mhz (osc1) - 12-bit adc number of channels 1 16 1 16 1 11 12-bit dac number of channels 1 4 1 4 1 2 7 32117ds?avr-01/12 at32uc3c analog comparators 4 4 2 jtag 1 awire 1 max frequency 66 mhz package lqfp144 tqfp 100 tqfp64/qfn64 table 2-1. configuration summary feature at32uc3c0512c/ at32uc3c0256c/ at32uc3c0128c/ at32uc3c064c at32uc3c1512c/ at32uc3c1256c/ AT32UC3C1128C/ at32uc3c164c at32uc3c2512c/ at32uc3c2256c/ at32uc3c2128c/ at32uc3c264c 8 32117ds?avr-01/12 at32uc3c 3. package and pinout 3.1 package the device pins are multiplexed with peripheral functions as described in table 3-1 on page 11 . figure 3-1. qfn64/tqfp64 pinout note: on qfn packages, the exposed pad is unconnected. pa00 1 pa01 2 pa02 3 pa03 4 vddio1 5 gndio1 6 pa04 7 pa05 8 pa06 9 pa07 10 pa08 11 pa09 12 pa16 13 adcvrefp 14 adcvrefn 15 pa19 16 gndana 17 vddana 18 pa20 19 pa21 20 pa22 21 pa23 22 vbus 23 dm 24 dp 25 gndpll 26 vddin_5 27 vddin_33 28 vddcore 29 gndcore 30 pb30 31 pb31 32 pd01 48 pd00 47 pc22 46 pc21 45 pc20 44 pc19 43 pc18 42 pc17 41 pc16 40 pc15 39 pc05 38 pc04 37 gndio2 36 vddio2 35 pc03 34 pc02 33 pd02 49 pd03 50 vddio3 51 gndio3 52 pd11 53 pd12 54 pd13 55 pd14 56 pd21 57 pd27 58 pd28 59 pd29 60 pd30 61 pb00 62 pb01 63 reset_n 64 9 32117ds?avr-01/12 at32uc3c figure 3-2. tqfp100 pinout pa00 1 pa01 2 pa02 3 pa03 4 vddio1 5 gndio1 6 pb04 7 pb05 8 pb06 9 pa04 10 pa05 11 pa06 12 pa07 13 pa08 14 pa09 15 pa10 16 pa11 17 pa12 18 pa13 19 pa14 20 pa15 21 pa16 22 adcvrefp 23 adcvrefn 24 pa19 25 gndana 26 vddana 27 pa20 28 pa21 29 pa22 30 pa23 31 pa24 32 pa25 33 vbus 34 dm 35 dp 36 gndpll 37 vddin_5 38 vddin_33 39 vddcore 40 gndcore 41 pb19 42 pb20 43 pb21 44 pb22 45 pb23 46 pb30 47 pb31 48 pc00 49 pc01 50 pd01 75 pd00 74 pc31 73 pc24 72 pc23 71 pc22 70 pc21 69 pc20 68 pc19 67 pc18 66 pc17 65 pc16 64 pc15 63 pc14 62 pc13 61 pc12 60 pc11 59 pc07 58 pc06 57 pc05 56 pc04 55 gndio2 54 vddio2 53 pc03 52 pc02 51 pd02 76 pd03 77 pd07 78 pd08 79 pd09 80 pd10 81 vddio3 82 gndio3 83 pd11 84 pd12 85 pd13 86 pd14 87 pd21 88 pd22 89 pd23 90 pd24 91 pd27 92 pd28 93 pd29 94 pd30 95 pb00 96 pb01 97 reset_n 98 pb02 99 pb03 100 10 32117ds?avr-01/12 at32uc3c figure 3-3. lqfp144 pinout pa00 1 pa01 2 pa02 3 pa03 4 vddio1 5 gndio1 6 pb04 7 pb05 8 pb06 9 pb07 10 pb08 11 pb09 12 pb10 13 pb11 14 pb12 15 pb13 16 pb14 17 pb15 18 pb16 19 pb17 20 pa04 21 pa05 22 pa06 23 pa07 24 pa08 25 pa09 26 pa10 27 pa11 28 pa12 29 pa13 30 pa14 31 pa15 32 pa16 33 adcvrefp 34 adcvrefn 35 pa19 36 gndana 37 vddana 38 pa20 39 pa21 40 pa22 41 pa23 42 pa24 43 pa25 44 pa26 45 pa27 46 pa28 47 pa29 48 vbus 49 dm 50 dp 51 gndpll 52 vddin_5 53 vddin_33 54 vddcore 55 gndcore 56 pb18 57 pb19 58 pb20 59 pb21 60 pb22 61 pb23 62 pb24 63 pb25 64 pb26 65 pb27 66 pb28 67 pb29 68 pb30 69 pb31 70 pc00 71 pc01 72 pd01 108 pd00 107 pc31 106 pc30 105 gndio3 104 vddio3 103 pc29 102 pc28 101 pc27 100 pc26 99 pc25 98 pc24 97 pc23 96 pc22 95 pc21 94 pc20 93 pc19 92 pc18 91 pc17 90 pc16 89 pc15 88 pc14 87 pc13 86 pc12 85 pc11 84 pc10 83 pc09 82 pc08 81 pc07 80 pc06 79 pc05 78 pc04 77 gndio2 76 vddio2 75 pc03 74 pc02 73 pd02 109 pd03 110 pd04 111 pd05 112 pd06 113 pd07 114 pd08 115 pd09 116 pd10 117 vddio3 118 gndio3 119 pd11 120 pd12 121 pd13 122 pd14 123 pd15 124 pd16 125 pd17 126 pd18 127 pd19 128 pd20 129 pd21 130 pd22 131 pd23 132 pd24 133 pd25 134 pd26 135 pd27 136 pd28 137 pd29 138 pd30 139 pb00 140 pb01 141 reset_n 142 pb02 143 pb03 144 11 32117ds?avr-01/12 at32uc3c 3.2 peripheral multiplexing on i/o lines 3.2.1 multiplexed signals each gpio line can be assigned to one of the peripheral functions. the following table describes the peripheral signals multiplexed to the gpio lines. table 3-1. gpio controller func tion multiplexing tqfp / qfn 64 tqfp 100 lqfp 144 pin g p i o supply pin type (1) gpio function abcde f 1 1 1 pa00 0 vddio1 x1/x2 canif - txline[1] 222pa011 vddio1 x1/x2 canif - rxline[1] pevc - pad_evt [0] 333pa022 vddio1 x1/x2 scif - gclk[0] pevc - pad_evt [1] 444pa033 vddio1 x1/x2 scif - gclk[1] eic - extint[1] 7 10 21 pa04 4 vddana x1/x2 adcin0 usbc - id acifa0 - acaout 8 11 22 pa05 5 vddana x1/x2 adcin1 usbc - vbof acifa0 - acbout 9 12 23 pa06 6 vddana x1/x2 adcin2 ac1ap1 pevc - pad_evt [2] 10 13 24 pa07 7 vddana x1/x2 adcin3 ac1an1 pevc - pad_evt [3] 11 14 25 pa08 8 vddana x1/x2 adcin4 ac1bp1 eic - extint[2] 12 15 26 pa09 9 vddana x1/x2 adcin5 ac1bn1 16 27 pa10 10 vddana x1/x2 adcin6 eic - extint[4] pevc - pad_evt [13] 17 28 pa11 11 vddana x1/x2 adcin7 adcref1 pevc - pad_evt [14] 18 29 pa12 12 vddana x1/x2 ac1ap0 spi0 - npcs[0] ac1ap0 or dac1a 19 30 pa13 13 vddana x1/x2 ac1an0 spi0 - npcs[1] adcin15 20 31 pa14 14 vddana x1/x2 ac1bp0 spi1 - npcs[0] 21 32 pa15 15 vddana x1/x2 ac1bn0 spi1 - npcs[1] ac1bn0 or dac1b 13 22 33 pa16 16 vddana x1/x2 adcref0 dacref 14 23 34 adc refp 15 24 35 adc refn 12 32117ds?avr-01/12 at32uc3c 16 25 36 pa19 19 vddana x1/x2 adcin8 eic - extint[1] 19 28 39 pa20 20 vddana x1/x2 adcin9 ac0ap0 ac0ap0 or dac0a 20 29 40 pa21 21 vddana x1/x2 adcin10 ac0bn0 ac0bn0 or dac0b 21 30 41 pa22 22 vddana x1/x2 adcin11 ac0an0 pevc - pad_evt [4] macb - speed 22 31 42 pa23 23 vddana x1/x2 adcin12 ac0bp0 pevc - pad_evt [5] macb - wol 32 43 pa24 24 vddana x1/x2 adcin13 spi1 - npcs[2] 33 44 pa25 25 vddana x1/x2 adcin14 spi1 - npcs[3] eic - extint[0] 45 pa26 26 vddana x1/x2 ac0ap1 eic - extint[1] 46 pa27 27 vddana x1/x2 ac0an1 eic - extint[2] 47 pa28 28 vddana x1/x2 ac0bp1 eic - extint[3] 48 pa29 29 vddana x1/x2 ac0bn1 eic - extint[0] 62 96 140 pb00 32 vddio1 x1 usart0 - clk canif - rxline[1] eic - extint[8] pevc - pad_evt [10] 63 97 141 pb01 33 vddio1 x1 canif - txline[1] pevc - pad_evt [11] 99 143 pb02 34 vddio1 x1 usbc - id pevc - pad_evt [6] tc1 - a1 100 144 pb03 35 vddio1 x1 usbc - vbof pevc - pad_evt [7] 7 7 pb04 36 vddio1 x1/x2 spi1 - mosi canif - rxline[0] qdec1 - qepi macb - txd[2] 8 8 pb05 37 vddio1 x1/x2 spi1 - miso canif - txline[0] pevc - pad_evt [12] usart3 - clk macb - txd[3] 9 9 pb06 38 vddio1 x2/x4 spi1 - sck qdec1 - qepa usart1 - clk macb - tx_er 10 pb07 39 vddio1 x1/x2 spi1 - npcs[0] eic - extint[2] qdec1 - qepb macb - rx_dv 11 pb08 40 vddio1 x1/x2 spi1 - npcs[1] pevc - pad_evt [1] pwm - pwml[0] macb - rxd[0] 12 pb09 41 vddio1 x1/x2 spi1 - npcs[2] pwm - pwmh[0] macb - rxd[1] 13 pb10 42 vddio1 x1/x2 usart1 - dtr spi0 - mosi pwm - pwml[1] table 3-1. gpio controller func tion multiplexing tqfp / qfn 64 tqfp 100 lqfp 144 pin g p i o supply pin type (1) gpio function abcde f 13 32117ds?avr-01/12 at32uc3c 14 pb11 43 vddio1 x1/x2 usart1 - dsr spi0 - miso pwm - pwmh[1] 15 pb12 44 vddio1 x1/x2 usart1 - dcd spi0 - sck pwm - pwml[2] 16 pb13 45 vddio1 x1/x2 usart1 - ri spi0 - npcs[0] pwm - pwmh[2] macb - rx_er 17 pb14 46 vddio1 x1/x2 usart1 - rts spi0 - npcs[1] pwm - pwml[3] macb - mdc 18 pb15 47 vddio1 x1/x2 usart1 - cts usart1 - clk pwm - pwmh[3] macb - mdio 19 pb16 48 vddio1 x1/x2 usart1 - rxd spi0 - npcs[2] pwm - ext_ faults[0] canif - rxline[0] 20 pb17 49 vddio1 x1/x2 usart1 - txd spi0 - npcs[3] pwm - ext_ faults[1] canif - txline[0] 57 pb18 50 vddio2 x1/x2 tc0 - clk2 eic - extint[4] 42 58 pb19 51 vddio2 x1/x2 tc0 - a0 spi1 - mosi iisc - isdo macb - crs 43 59 pb20 52 vddio2 x1/x2 tc0 - b0 spi1 - miso iisc - isdi acifa1 - acaout macb - col 44 60 pb21 53 vddio2 x2/x4 tc0 - clk1 spi1 - sck iisc - imck acifa1 - acbout macb - rxd[2] 45 61 pb22 54 vddio2 x1/x2 tc0 - a1 spi1 - npcs[3] iisc - isck scif - gclk[0] macb - rxd[3] 46 62 pb23 55 vddio2 x1/x2 tc0 - b1 spi1 - npcs[2] iisc - iws scif - gclk[1] macb - rx_clk 63 pb24 56 vddio2 x1/x2 tc0 - clk0 spi1 - npcs[1] 64 pb25 57 vddio2 x1/x2 tc0 - a2 spi1 - npcs[0] pevc - pad_evt [8] 65 pb26 58 vddio2 x2/x4 tc0 - b2 spi1 - sck pevc - pad_evt [9] macb - tx_en 66 pb27 59 vddio2 x1/x2 qdec0 - qepa spi1 - miso pevc - pad_evt [10] tc1 - clk0 macb - txd[0] 67 pb28 60 vddio2 x1/x2 qdec0 - qepb spi1 - mosi pevc - pad_evt [11] tc1 - b0 macb - txd[1] 68 pb29 61 vddio2 x1/x2 qdec0 - qepi spi0 - npcs[0] pevc - pad_evt [12] tc1 - a0 31 47 69 pb30 62 vddio2 x1 32 48 70 pb31 63 vddio2 x1 49 71 pc00 64 vddio2 x1/x2 usbc - id spi0 - npcs[1] usart2 - cts tc1 - b2 canif - txline[1] 50 72 pc01 65 vddio2 x1/x2 usbc - vbof spi0 - npcs[2] usart2 - rts tc1 - a2 canif - rxline[1] table 3-1. gpio controller func tion multiplexing tqfp / qfn 64 tqfp 100 lqfp 144 pin g p i o supply pin type (1) gpio function abcde f 14 32117ds?avr-01/12 at32uc3c 33 51 73 pc02 66 vddio2 x1 twims0 - twd spi0 - npcs[3] usart2 - rxd tc1 - clk1 macb - mdc 34 52 74 pc03 67 vddio2 x1 twims0 - twck eic - extint[1] usart2 - txd tc1 - b1 macb - mdio 37 55 77 pc04 68 vddio2 x1 twims1 - twd eic - extint[3] usart2 - txd tc0 - b1 38 56 78 pc05 69 vddio2 x1 twims1 - twck eic - extint[4] usart2 - rxd tc0 - a2 57 79 pc06 70 vddio2 x1 pevc - pad_evt [15] usart2 - clk usart2 - cts tc0 - clk2 twims2 - twd twims0 - twalm 58 80 pc07 71 vddio2 x1 pevc - pad_evt [2] ebi - ncs[3] usart2 - rts tc0 - b2 twims2 - twck twims1 - twalm 81 pc08 72 vddio2 x1/x2 pevc - pad_evt [13] spi1 - npcs[1] ebi - ncs[0] usart4 - txd 82 pc09 73 vddio2 x1/x2 pevc - pad_evt [14] spi1 - npcs[2] ebi - addr[23] usart4 - rxd 83 pc10 74 vddio2 x1/x2 pevc - pad_evt [15] spi1 - npcs[3] ebi - addr[22] 59 84 pc11 75 vddio2 x1/x2 pwm - pwmh[3] canif - rxline[1] ebi - addr[21] tc0 - clk0 60 85 pc12 76 vddio2 x1/x2 pwm - pwml[3] canif - txline[1] ebi - addr[20] usart2 - clk 61 86 pc13 77 vddio2 x1/x2 pwm - pwmh[2] eic - extint[7] usart0 - rts 62 87 pc14 78 vddio2 x1/x2 pwm - pwml[2] usart0 - clk ebi - sdcke usart0 - cts 39 63 88 pc15 79 vddio2 x1/x2 pwm - pwmh[1] spi0 - npcs[0] ebi - sdwe usart0 - rxd canif - rxline[1] 40 64 89 pc16 80 vddio2 x1/x2 pwm - pwml[1] spi0 - npcs[1] ebi - cas usart0 - txd canif - txline[1] 41 65 90 pc17 81 vddio2 x1/x2 pwm - pwmh[0] spi0 - npcs[2] ebi - ras iisc - isdo usart3 - txd 42 66 91 pc18 82 vddio2 x1/x2 pwm - pwml[0] eic - extint[5] ebi - sda10 iisc - isdi usart3 - rxd 43 67 92 pc19 83 vddio3 x1/x2 pwm - pwml[2] scif - gclk[0] ebi - data[0] iisc - imck usart3 - cts 44 68 93 pc20 84 vddio3 x1/x2 pwm - pwmh[2] scif - gclk[1] ebi - data[1] iisc - isck usart3 - rts 45 69 94 pc21 85 vddio3 x1/x2 pwm - ext_ faults[0] canif - rxline[0] ebi - data[2] iisc - iws 46 70 95 pc22 86 vddio3 x1/x2 pwm - ext_ faults[1] canif - txline[0] ebi - data[3] usart3 - clk 71 96 pc23 87 vddio3 x1/x2 qdec1 - qepb canif - rxline[1] ebi - data[4] pevc - pad_evt [3] table 3-1. gpio controller func tion multiplexing tqfp / qfn 64 tqfp 100 lqfp 144 pin g p i o supply pin type (1) gpio function abcde f 15 32117ds?avr-01/12 at32uc3c 72 97 pc24 88 vddio3 x1/x2 qdec1 - qepa canif - txline[1] ebi - data[5] pevc - pad_evt [4] 98 pc25 89 vddio3 x1/x2 tc1 - clk2 ebi - data[6] scif - gclk[0] usart4 - txd 99 pc26 90 vddio3 x1/x2 qdec1 - qepi tc1 - b2 ebi - data[7] scif - gclk[1] usart4 - rxd 100 pc27 91 vddio3 x1/x2 tc1 - a2 ebi - data[8] eic - extint[0] usart4 - cts 101 pc28 92 vddio3 x1/x2 spi1 - npcs[3] tc1 - clk1 ebi - data[9] usart4 - rts 102 pc29 93 vddio3 x1/x2 spi0 - npcs[1] tc1 - b1 ebi - data[10] 105 pc30 94 vddio3 x1/x2 spi0 - npcs[2] tc1 - a1 ebi - data[11] 73 106 pc31 95 vddio3 x1/x2 spi0 - npcs[3] tc1 - b0 ebi - data[12] pevc - pad_evt [5] usart4 - clk 47 74 107 pd00 96 vddio3 x1/x2 spi0 - mosi tc1 - clk0 ebi - data[13] qdec0 - qepi usart0 - txd 48 75 108 pd01 97 vddio3 x1/x2 spi0 - miso tc1 - a0 ebi - data[14] tc0 - clk1 usart0 - rxd 49 76 109 pd02 98 vddio3 x2/x4 spi0 - sck tc0 - clk2 ebi - data[15] qdec0 - qepa 50 77 110 pd03 99 vddio3 x1/x2 spi0 - npcs[0] tc0 - b2 ebi - addr[0] qdec0 - qepb 111 pd04 100 vddio3 x1/x2 spi0 - mosi ebi - addr[1] 112 pd05 101 vddio3 x1/x2 spi0 - miso ebi - addr[2] 113 pd06 102 vddio3 x2/x4 spi0 - sck ebi - addr[3] 78 114 pd07 103 vddio3 x1/x2 usart1 - dtr eic - extint[5] ebi - addr[4] qdec0 - qepi usart4 - txd 79 115 pd08 104 vddio3 x1/x2 usart1 - dsr eic - extint[6] ebi - addr[5] tc1 - clk2 usart4 - rxd 80 116 pd09 105 vddio3 x1/x2 usart1 - dcd canif - rxline[0] ebi - addr[6] qdec0 - qepa usart4 - cts 81 117 pd10 106 vddio3 x1/x2 usart1 - ri canif - txline[0] ebi - addr[7] qdec0 - qepb usart4 - rts 53 84 120 pd11 107 vddio3 x1/x2 usart1 - txd usbc - id ebi - addr[8] pevc - pad_evt [6] macb - txd[0] 54 85 121 pd12 108 vddio3 x1/x2 usart1 - rxd usbc - vbof ebi - addr[9] pevc - pad_evt [7] macb - txd[1] 55 86 122 pd13 109 vddio3 x2/x4 usart1 - cts usart1 - clk ebi - sdck pevc - pad_evt [8] macb - rxd[0] 56 87 123 pd14 110 vddio3 x1/x2 usart1 - rts eic - extint[7] ebi - addr[10] pevc - pad_evt [9] macb - rxd[1] table 3-1. gpio controller func tion multiplexing tqfp / qfn 64 tqfp 100 lqfp 144 pin g p i o supply pin type (1) gpio function abcde f 16 32117ds?avr-01/12 at32uc3c note: 1. refer to ?electrical characteristics? on page 50 for a description of the electrical properties of the pin types used. see section 3.3 for a description of the various peripheral signals. 3.2.2 peripheral functions each gpio line can be assigned to one of several peripheral functions. the following table describes how the various peripheral functions are selected. the last listed function has priority in case multiple functions are enabled on the same pin. 124 pd15 111 vddio3 x1/x2 tc0 - a0 usart3 - txd ebi - addr[11] 125 pd16 112 vddio3 x1/x2 tc0 - b0 usart3 - rxd ebi - addr[12] 126 pd17 113 vddio3 x1/x2 tc0 - a1 usart3 - cts ebi - addr[13] usart3 - clk 127 pd18 114 vddio3 x1/x2 tc0 - b1 usart3 - rts ebi - addr[14] 128 pd19 115 vddio3 x1/x2 tc0 - a2 ebi - addr[15] 129 pd20 116 vddio3 x1/x2 tc0 - b2 ebi - addr[16] 57 88 130 pd21 117 vddio3 x1/x2 usart3 - txd eic - extint[0] ebi - addr[17] qdec1 - qepi 89 131 pd22 118 vddio1 x1/x2 usart3 - rxd tc0 - a2 ebi - addr[18] scif - gclk[0] 90 132 pd23 119 vddio1 x1/x2 usart3 - cts usart3 - clk ebi - addr[19] qdec1 - qepa 91 133 pd24 120 vddio1 x1/x2 usart3 - rts eic - extint[8] ebi - nwe1 qdec1 - qepb 134 pd25 121 vddio1 x1/x2 tc0 - clk0 usbc - id ebi - nwe0 usart4 - clk 135 pd26 122 vddio1 x1/x2 tc0 - clk1 usbc - vbof ebi - nrd 58 92 136 pd27 123 vddio1 x1/x2 usart0 - txd canif - rxline[0] ebi - ncs[1] tc0 - a0 macb - rx_er 59 93 137 pd28 124 vddio1 x1/x2 usart0 - rxd canif - txline[0] ebi - ncs[2] tc0 - b0 macb - rx_dv 60 94 138 pd29 125 vddio1 x1/x2 usart0 - cts eic - extint[6] usart0 - clk tc0 - clk0 macb - tx_clk 61 95 139 pd30 126 vddio1 x1/x2 usart0 - rts eic - extint[3] ebi - nwait tc0 - a1 macb - tx_en table 3-1. gpio controller func tion multiplexing tqfp / qfn 64 tqfp 100 lqfp 144 pin g p i o supply pin type (1) gpio function abcde f table 3-2. peripheral functions function description gpio controller function multiplexing gpio and gpio peripheral selection a to f nexus ocd aux port connections ocd trace system 17 32117ds?avr-01/12 at32uc3c 3.2.3 oscillator pinout the oscillators are not mapped to the normal gp io functions and their muxings are controlled by registers in the system control interface (scif). please refer to the scif chapter for more information about this. 3.2.4 jtag port connections if the jtag is enabled, the jtag will take control over a number of pins, irrespectively of the i/o controller configuration. 3.2.5 nexus ocd aux port connections if the ocd trace system is enabled, the trace system will take control over a number of pins, irre- spectively of the gpio configuration. three different ocd trace pin mappings are possible, awire dataout awire output in two-pin mode jtag port connections jtag debug port oscillators osc0, osc32 table 3-2. peripheral functions function description table 3-3. oscillator pinout qfn64/ tqfp64 pin tqfp100 pin lqfp144 pin pad oscillator pin 31 47 69 pb30 xin0 99 143 pb02 xin1 62 96 140 pb00 xin32 32 48 70 pb31 xout0 100 144 pb03 xout1 63 97 141 pb01 xout32 table 3-4. jtag pinout qfn64/ tqfp64 pin tqfp100 pin lqfp144 pin pin name jtag pin 222pa01tdi 333pa02tdo 444pa03tms 111pa00tck 18 32117ds?avr-01/12 at32uc3c depending on the configuration of the ocd axs register. for details, see the avr32uc techni- cal reference manual . 3.2.6 other functions the functions listed in table 3-6 are not mapped to the normal gpio functions. the awire data pin will only be active after the awire is e nabled. the awire dataout pin will only be active after the awire is enabled and the 2_pin_mode command has been sent. 3.3 signals description the following table give details on the signal name classified by peripherals. table 3-5. nexus ocd aux port connections pin axs=0 axs=1 axs=2 evti_n pa08 pb19 pa10 mdo[5] pc05 pc31 pb06 mdo[4] pc04 pc12 pb15 mdo[3] pa23 pc11 pb14 mdo[2] pa22 pb23 pa27 mdo[1] pa19 pb22 pa26 mdo[0] pa09 pb20 pa19 evto_n pd29 pd29 pd29 mcko pd13 pb21 pb26 mseo[1] pd30 pd08 pb25 mseo[0] pd14 pd07 pb18 table 3-6. other functions qfn64/ tqfp64 pin tqfp100 pin lqfp144 pin pad oscillator pin 64 98 142 reset_n awire data 333pa02awire dataout table 3-7. signal description list signal name function type active level comments power vddio1 vddio2 vddio3 i/o power supply power input 4.5v to 5.5v or 3.0v to 3.6 v vddana analog power supply power input 4.5v to 5.5v or 3.0v to 3.6 v 19 32117ds?avr-01/12 at32uc3c vddin_5 1.8v voltage regulator input power input power supply: 4.5v to 5.5v or 3.0v to 3.6 v vddin_33 usb i/o power supply power output/ input capacitor connection for the 3.3v voltage regulator or power supply: 3.0v to 3.6 v vddcore 1.8v voltage regulator output power output capacitor connection for the 1.8v voltage regulator gndio1 gndio2 gndio3 i/o ground ground gndana analog ground ground gndcore ground of the core ground gndpll ground of the plls ground analog comparator interface - acifa0/1 ac0an1/ac0an0 negative inputs for comparator ac0a analog ac0ap1/ac0ap0 positive inputs for comparator ac0a analog ac0bn1/ac0bn0 negative inputs for comparator ac0b analog ac0bp1/ac0bp0 positive inputs for comparator ac0b analog ac1an1/ac1an0 negative inputs for comparator ac1a analog ac1ap1/ac1ap0 positive inputs for comparator ac1a analog ac1bn1/ac1bn0 negative inputs for comparator ac1b analog ac1bp1/ac1bp0 positive inputs for comparator ac1b analog acaout/acbout analog comparator outputs output adc interface - adcifa adcin[15:0] adc input pins analog adcref0 analog positive reference 0 voltage input analog adcref1 analog positive reference 1 voltage input analog adcvrefp analog positive reference connected to external capacitor analog table 3-7. signal description list signal name function type active level comments 20 32117ds?avr-01/12 at32uc3c adcvrefn analog negative reference connected to external capacitor analog auxiliary port - aux mcko trace data output clock output mdo[5:0] trace data output output mseo[1:0] trace frame control output evti_n event in output low evto_n event out output low awire - aw data awire data i/o dataout awire data output for 2-pin mode i/o controller area network interface - canif rxline[1:0] can channel rxline i/o txline[1:0] can channel txline i/o dac interface - dacifb0/1 dac0a, dac0b dac0 output pins of s/h a analog dac1a, dac1b dac output pins of s/h b analog dacref analog reference voltage input analog external bus interface - ebi addr[23:0] address bus output cas column signal output low data[15:0] data bus i/o ncs[3:0] chip select output low nrd read signal output low nwait external wait signal input low nwe0 write enable 0 output low nwe1 write enable 1 output low ras row signal output low sda10 sdram address 10 line output table 3-7. signal description list signal name function type active level comments 21 32117ds?avr-01/12 at32uc3c sdck sdram clock output sdcke sdram clock enable output sdwe sdram write enable output low external interrup t controller - eic extint[8:1] external interrupt pins input nmi_n = extint[0] non-maskable interrupt pin input low general purpose input/output - gpioa, gpiob, gpioc, gpiod pa[29:19] - pa[16:0] parallel i/o controller gpioa i/o pb[31:0] parallel i/o controller gpiob i/o pc[31:0] parallel i/o controller gpioc i/o pd[30:0] parallel i/o controller gpiod i/o inter-ic sound (i2s) controller - iisc imck i2s master clock output isck i2s serial clock i/o isdi i2s serial data in input isdo i2s serial data out output iws i2s word select i/o jtag tck test clock input tdi test data in input tdo test data out output tms test mode select input ethernet mac - macb col collision detect input crs carrier sense and data valid input mdc management data clock output mdio management data input/output i/o rxd[3:0] receive data input table 3-7. signal description list signal name function type active level comments 22 32117ds?avr-01/12 at32uc3c rx_clk receive clock input rx_dv receive data valid input rx_er receive coding error input speed speed output txd[3:0] transmit data output tx_clk transmit clock or reference clock input tx_en transmit enable output tx_er transmit coding error output wol wake-on-lan output peripheral event controller - pevc pad_evt[15:0] event input pins input power manager - pm reset_n reset pin input low pulse width modulator - pwm pwmh[3:0] pwml[3:0] pwm output pins output ext_fault[1:0] pwm fault input pins input quadrature decoder- qdec0/qdec1 qepa qepa quadrature input input qepb qepb quadrature input input qepi index input input system controller interface- scif xin0, xin1, xin32 crystal 0, 1, 32k inputs analog xout0, xout1, xout32 crystal 0, 1, 32k output analog gclk0 - gclk1 generic clock pins output serial peripheral in terface - spi0, spi1 miso master in slave out i/o mosi master out slave in i/o table 3-7. signal description list signal name function type active level comments 23 32117ds?avr-01/12 at32uc3c npcs[3:0] spi peripheral chip select i/o low sck clock output timer/counter - tc0, tc1 a0 channel 0 line a i/o a1 channel 1 line a i/o a2 channel 2 line a i/o b0 channel 0 line b i/o b1 channel 1 line b i/o b2 channel 2 line b i/o clk0 channel 0 external clock input input clk1 channel 1 external clock input input clk2 channel 2 external clock input input two-wire interface - twims0, twims1, twims2 twalm smbus smbalert i/o low only on twims0, twims1 twck serial clock i/o twd serial data i/o universal synchronous asynchronous receiver tran smitter - usart0, usart1, usart2, usart3, usart4 clk clock i/o cts clear to send input low dcd data carrier detect input low only usart1 dsr data set ready input low only usart1 dtr data terminal ready output low only usart1 ri ring indicator input low only usart1 rts request to send output low rxd receive data input txd transmit data output universal serial bus device - usb dm usb device port data - analog table 3-7. signal description list signal name function type active level comments 24 32117ds?avr-01/12 at32uc3c 3.4 i/o line considerations 3.4.1 jtag pins the jtag is enabled if tck is low while the reset_n pin is re leased. the tck, tms, and tdi pins have pull-up resistors when jtag is enabled. the tck pin always have pull-up enabled during reset. the tdo pin is an output, driven at vddio1, and has no pull-up resistor. the jtag pins can be used as gpio pins and muxed with peripherals when the jtag is disabled. please refer to section 3.2.4 for the jtag port connections. 3.4.2 reset_n pin the reset_n pin integrates a pull- up resistor to vddio1. as t he product integr ates a power-on reset cell, the reset_n pin can be left unconnected in case no reset from the system needs to be applied to the product. the reset_n pin is also used for the awire de bug protocol. when the pin is used for debug- ging, it must not be driven by external circuitry. 3.4.3 twi pins when these pins are used for twi, the pins are open-drain outputs with slew-rate limitation and inputs with inputs with spike-filtering. when used as gpio-pins or used for other peripherals, the pins have the same charac teristics as gpio pins. 3.4.4 gpio pins all i/o lines integrate programmable pull-up and pul l-down resistors. most i/o lines integrate drive strength control, see table 3-1 . programming of this pull-up and pull-down resistor or this drive strength is performed independently for each i/o line through the gpio controllers. after reset, i/o lines default as inputs with pull-up/ pull-down resistors disabled. after reset, out- put drive strength is configured to the lowest value to reduce global emi of the device. when the i/o line is configured as analog func tion (adc i/o, ac inputs, dac i/o), the pull-up and pull-down resistors are automatically disabled. dp usb device port data + analog vbus usb vbus monitor and otg negociation analog input id id pin of the usb bus input vbof usb vbus on/off: bus power control port output table 3-7. signal description list signal name function type active level comments 25 32117ds?avr-01/12 at32uc3c 4. processor and architecture rev: 2.1.2.0 this chapter gives an overview of the avr32uc cpu. avr32uc is an implementation of the avr32 architecture. a summary of the programming model, instruction set, and mpu is pre- sented. for further details, see the avr32 architecture manual and the avr32uc technical reference manual . 4.1 features ? 32-bit load/store avr32a risc architecture ? 15 general-purpose 32-bit registers ? 32-bit stack pointer, program counter and link register reside in register file ? fully orthogonal instruction set ? privileged and unprivileged modes enabling efficient and secure operating systems ? innovative instruction set together with variable instruction length ensu ring industry leading code density ? dsp extension with saturating arithmetic, and a wide variety of multiply instructions ? 3-stage pipeline allowing one instruction per clock cy cle for most instructions ? byte, halfword, word, and double word memory access ? multiple interrupt priority levels ? mpu allows for operating s ystems with memory protection ? fpu enables hardware accelerate d floating poin t calculations ? secure state for supporting flashvault technology 4.2 avr32 architecture avr32 is a new, high-performance 32-bit risc mi croprocessor architectu re, designed for cost- sensitive embedded applications, with particul ar emphasis on low power consumption and high code density. in addition, the instruction set architecture has been tuned to allow a variety of microarchitectures, enabling the avr32 to be implemented as low-, mid-, or high-performance processors. avr32 extends the avr family into the world of 32- and 64-bit applications. through a quantitative approach, a large set of industry recognized benchmarks has been com- piled and analyzed to achieve the best code density in its class. in addition to lowering the memory requirements, a compact code size also contributes to the core?s low power characteris- tics. the processor supports byte and halfword data types without penalty in code size and performance. memory load and store operations are provided for byte, halfword, word, and double word data with automatic sign- or zero extension of halfw ord and byte data. the c-compiler is closely linked to the architecture and is able to expl oit code optimization features, both for size and speed. in order to reduce code size to a minimum, so me instructions have multiple addressing modes. as an example, instructions with immediates often have a compact format with a smaller imme- diate, and an extended format with a larger immediate. in this way, the compiler is able to use the format giving the smallest code size. another feature of the instruction set is that frequently used instructions, like add, have a com- pact format with two operands as well as an extended format with three operands. the larger format increases performance, allowing an addition and a data move in the same instruction in a 26 32117ds?avr-01/12 at32uc3c single cycle. load and store instructions have seve ral different formats in order to reduce code size and speed up execution. the register file is organized as sixteen 32-bi t registers and includes the program counter, the link register, and the stack pointer. in addition, register r12 is designed to hold return values from function calls and is used im plicitly by some instructions. 4.3 the avr32uc cpu the avr32uc cpu targets low- and mediu m-performance applications, and provides an advanced on-chip debug (ocd) system, no caches , and a memory protection unit (mpu). a hardware floating point unit (fpu) is also pr ovided through the coprocessor instruction space. java acceleration hardware is not implemented. avr32uc provides three memory interfaces, one high speed bus master for instruction fetch, one high speed bus master for data access, an d one high speed bus slave interface allowing other bus masters to access data rams internal to the cpu. keeping data rams internal to the cpu allows fast access to the rams, reduces latency, and guarantees deterministic timing. also, power consumption is reduced by not needing a full high speed bus access for memory accesses. a dedicated data ram interface is prov ided for communicating with the internal data rams. a local bus interface is provided for connecting the cpu to device-specific high-speed systems, such as floating-point units and i/o controller port s. this local bus has to be enabled by writing a one to the locen bit in the cpucr system regi ster. the local bus is able to transfer data between the cpu and the local bus slave in a single clock cycle. the local bus has a dedicated memory range allocated to it, and data transfers are performed using regular load and store instructions. details on which devices that are mapped into the local bus space is given in the cpu local bus section in the memories chapter. figure 4-1 on page 27 displays the contents of avr32uc. 27 32117ds?avr-01/12 at32uc3c figure 4-1. overview of the avr32uc cpu 4.3.1 pipeline overview avr32uc has three pipeline stages, instruction fetch (if), instruction decode (id), and instruc- tion execute (ex). the ex stage is split into three parallel subsections, one arithmetic/logic (alu) section, one multiply (mul) sect ion, and one load/store (ls) section. instructions are issued and complete in order. certain operations require several clock cycles to complete, and in this case, the instruction resides in the id and ex stages for the required num- ber of clock cycles. since there is only three pipeline stages, no inte rnal data forwarding is required, and no data dependencies can arise in the pipeline. figure 4-2 on page 28 shows an overview of the avr32uc pipeline stages. avr32uc cpu pipeline instruction memory controller mpu high speed bus high speed bus ocd system ocd interface interrupt controller interface high speed bus slave high speed bus high speed bus master power/ reset control reset interface cpu local bus master cpu local bus data memory controller cpu ram high speed bus master 28 32117ds?avr-01/12 at32uc3c figure 4-2. the avr32uc pipeline 4.3.2 avr32a microarchitecture compliance avr32uc implements an avr32a microarchitecture. the avr32a microarchitecture is tar- geted at cost-sensitive, lower-end applications like smaller microcontrollers. this microarchitecture does not provide dedicated hard ware registers for shadowing of register file registers in interrupt contexts. additionally, it does not provide hardware registers for the return address registers and return status registers. instead, all this information is stored on the system stack. this saves chip area at the expense of slower interrupt handling. 4.3.2.1 interrupt handling upon interrupt initiation, registers r8-r12 are automatically pushed to the system stack. these registers are pushed regardless of the priority level of the pending interrupt. the return address and status register are also automatically pushed to stack. the interrupt handler can therefore use r8-r12 freely. upon interrupt completion, the old r8-r12 registers and status register are restored, and execution continues at the return address stored popped from stack. the stack is also used to store the status register and return address for exceptions and scall . executing the rete or rets instruction at the completion of an exception or system call will pop this status register and continue execution at the popped return address. 4.3.2.2 java support avr32uc does not provide java hardware acceleration. 4.3.2.3 floating point support a fused multiply-accumulate floa ting point unit (fpu), perfor maing a multiply and accumulate as a single operation with no intermediate rounding, therby increasing precision is provided. the floating point hardware conforms to the requirements of the c standard, which is based on the ieee 754 floating point standard. 4.3.2.4 memory protection the mpu allows the user to check all memory accesses for privilege violations. if an access is attempted to an illegal memory address, the access is aborted and an exception is taken. the mpu in avr32uc is specified in t he avr32uc technical reference manual. if id alu mul regfile write prefetch unit decode unit alu unit multiply unit load-store unit ls regfile read 29 32117ds?avr-01/12 at32uc3c 4.3.2.5 unaligned reference handling avr32uc does not support unaligned accesses, except for doubleword accesses. avr32uc is able to perform word-aligned st.d and ld.d . any other unaligned memory access will cause an address exception. doubleword -sized accesses with word-align ed pointers will automatically be performed as two word-sized accesses. the following table shows the instructions with support for unaligned addresses. all other instructions requir e aligned addresses. 4.3.2.6 unimplemented instructions the following instructions are unimplemented in avr32uc, and will cause an unimplemented instruction exception if executed: ? all simd instructions ? all coprocessor instructions if no coprocessors are present ? retj, incjosp, popjc, pushjc ? tlbr, tlbs, tlbw ? cache 4.3.2.7 cpu and architecture revision three major revisions of the avr32uc cpu currently exist. the device described in this datasheet uses cpu revision 3. the architecture revision field in the config0 system register identifies which architecture revision is implemented in a specific device. avr32uc cpu revision 3 is fully backward-compatibl e with revisions 1 and 2, ie. code compiled for revision 1 or 2 is binary-compatible with revision 3 cpus. table 4-1. instructions with una ligned reference support instruction supported alignment ld.d word st.d word 30 32117ds?avr-01/12 at32uc3c 4.4 programming model 4.4.1 register file configuration the avr32uc register file is shown below. figure 4-3. the avr32uc register file 4.4.2 status register configuration the status register (sr) is split into two halfwords, one upper and one lower, see figure 4-4 and figure 4-5 . the lower word contains the c, z, n, v, and q condition code flags and the r, t, and l bits, while the upper halfword contains information about the mode and state the proces- sor executes in. refer to the avr32 architecture manual for details. figure 4-4. the status register high halfword application bit 0 supervisor bit 31 pc sr int0pc fintpc int1pc smpc r7 r5 r6 r4 r3 r1 r2 r0 bit 0 bit 31 pc sr r12 int0pc fintpc int1pc smpc r7 r5 r6 r4 r11 r9 r10 r8 r3 r1 r2 r0 int0 sp_app sp_sys r12 r11 r9 r10 r8 exception nmi int1 int2 int3 lr lr bit 0 bit 31 pc sr r12 int0pc fintpc int1pc smpc r7 r5 r6 r4 r11 r9 r10 r8 r3 r1 r2 r0 sp_sys lr bit 0 bit 31 pc sr r12 int0pc fintpc int1pc smpc r7 r5 r6 r4 r11 r9 r10 r8 r3 r1 r2 r0 sp_sys lr bit 0 bit 31 pc sr r12 int0pc fintpc int1pc smpc r7 r5 r6 r4 r11 r9 r10 r8 r3 r1 r2 r0 sp_sys lr bit 0 bit 31 pc sr r12 int0pc fintpc int1pc smpc r7 r5 r6 r4 r11 r9 r10 r8 r3 r1 r2 r0 sp_sys lr bit 0 bit 31 pc sr r12 int0pc fintpc int1pc smpc r7 r5 r6 r4 r11 r9 r10 r8 r3 r1 r2 r0 sp_sys lr bit 0 bit 31 pc sr r12 int0pc fintpc int1pc smpc r7 r5 r6 r4 r11 r9 r10 r8 r3 r1 r2 r0 sp_sys lr secure bit 0 bit 31 pc sr r12 int0pc fintpc int1pc smpc r7 r5 r6 r4 r11 r9 r10 r8 r3 r1 r2 r0 sp_sec lr ss_status ss_adrf ss_adrr ss_adr0 ss_adr1 ss_sp_sys ss_sp_app ss_rar ss_rsr bit 31 0 0 0 bit 16 interrupt level 0 mask interrupt level 1 mask interrupt level 3 mask interrupt level 2 mask 1 0 0 0 0 1 1 0 0 0 0 0 0 fe i0m gm m1 - d m0 em i2m dm - m2 lc 1 ss initial value bit name i1m mode bit 0 mode bit 1 - mode bit 2 reserved debug state - i3m reserved exception mask global interrupt mask debug state mask secure state 31 32117ds?avr-01/12 at32uc3c figure 4-5. the status register low halfword 4.4.3 processor states 4.4.3.1 normal risc state the avr32 processor supports several diff erent execution contexts as shown in table 4-2 . mode changes can be made under software control, or can be caused by external interrupts or exception processing. a mode can be interrupted by a higher priority mode, but never by one with lower priority. nested exceptions can be supported with a minimal software overhead. when running an operating system on the avr32, user processes will typically execute in the application mode. the programs executed in this mode are restricted from executing certain instructions. furthermore, most system registers together with the upper halfword of the status register cannot be accessed. protected memory areas are also not available. all other operating modes are privileged and are collectively called system modes. they have full access to all priv- ileged and unprivileged re sources. after a reset, the proc essor will be in su pervisor mode. 4.4.3.2 debug state the avr32 can be set in a debug state, which allows implementation of software monitor rou- tines that can read out and alter system information for use during application development. this implies that all system and application regist ers, including the status registers and program counters, are accessible in debug state. th e privileged instructions are also available. all interrupt levels are by default disabled when debug state is entered, but they can individually be switched on by the monitor routine by clearing the respective mask bit in the status register. bit 15 bit 0 reserved carry zero sign 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - - - - t - bit name initial value 0 0 l q v n z c - overflow saturation - - - lock reserved scratch table 4-2. overview of execution modes, thei r priorities and privilege levels. priority mode securi ty description 1 non maskable interrupt privileged non maskable high priority interrupt mode 2 exception privileged execute exceptions 3 interrupt 3 privileged general purpose interrupt mode 4 interrupt 2 privileged general purpose interrupt mode 5 interrupt 1 privileged general purpose interrupt mode 6 interrupt 0 privileged general purpose interrupt mode n/a supervisor privileged runs supervisor calls n/a application unprivileged normal program execution mode 32 32117ds?avr-01/12 at32uc3c debug state can be entered as described in the avr32uc technical reference manual . debug state is exited by the retd instruction. 4.4.3.3 secure state the avr32 can be set in a secure state, that allows a part of the code to execute in a state with higher security levels. the rest of the code can not access resources reserved for this secure code. secure state is used to implemen t flashvault technology. refer to the avr32uc techni- cal reference manual for details. 4.4.4 system registers the system registers are placed outside of the virtual memory space, and are only accessible using the privileged mfsr and mtsr instructions. the table below lis ts the system registers speci- fied in the avr32 architecture, some of which are unused in avr32uc. the programmer is responsible for maintaining correct sequen cing of any instructions following a mtsr instruction. for detail on the system registers, refer to the avr32uc technical reference manual . table 4-3. system registers reg # address name function 0 0 sr status register 1 4 evba exception vector base address 2 8 acba application call base address 3 12 cpucr cpu control register 4 16 ecr exception cause register 5 20 rsr_sup unused in avr32uc 6 24 rsr_int0 unused in avr32uc 7 28 rsr_int1 unused in avr32uc 8 32 rsr_int2 unused in avr32uc 9 36 rsr_int3 unused in avr32uc 10 40 rsr_ex unused in avr32uc 11 44 rsr_nmi unused in avr32uc 12 48 rsr_dbg return status register for debug mode 13 52 rar_sup unused in avr32uc 14 56 rar_int0 unused in avr32uc 15 60 rar_int1 unused in avr32uc 16 64 rar_int2 unused in avr32uc 17 68 rar_int3 unused in avr32uc 18 72 rar_ex unused in avr32uc 19 76 rar_nmi unused in avr32uc 20 80 rar_dbg return address register for debug mode 21 84 jecr unused in avr32uc 22 88 josp unused in avr32uc 23 92 java_lv0 unused in avr32uc 33 32117ds?avr-01/12 at32uc3c 24 96 java_lv1 unused in avr32uc 25 100 java_lv2 unused in avr32uc 26 104 java_lv3 unused in avr32uc 27 108 java_lv4 unused in avr32uc 28 112 java_lv5 unused in avr32uc 29 116 java_lv6 unused in avr32uc 30 120 java_lv7 unused in avr32uc 31 124 jtba unused in avr32uc 32 128 jbcr unused in avr32uc 33-63 132-252 reserved reserved for future use 64 256 config0 configuration register 0 65 260 config1 configuration register 1 66 264 count cycle counter register 67 268 compare compare register 68 272 tlbehi unused in avr32uc 69 276 tlbelo unused in avr32uc 70 280 ptbr unused in avr32uc 71 284 tlbear unused in avr32uc 72 288 mmucr unused in avr32uc 73 292 tlbarlo unused in avr32uc 74 296 tlbarhi unused in avr32uc 75 300 pccnt unused in avr32uc 76 304 pcnt0 unused in avr32uc 77 308 pcnt1 unused in avr32uc 78 312 pccr unused in avr32uc 79 316 bear bus error address register 80 320 mpuar0 mpu address register region 0 81 324 mpuar1 mpu address register region 1 82 328 mpuar2 mpu address register region 2 83 332 mpuar3 mpu address register region 3 84 336 mpuar4 mpu address register region 4 85 340 mpuar5 mpu address register region 5 86 344 mpuar6 mpu address register region 6 87 348 mpuar7 mpu address register region 7 88 352 mpupsr0 mpu privilege select register region 0 89 356 mpupsr1 mpu privilege select register region 1 table 4-3. system registers (continued) reg # address name function 34 32117ds?avr-01/12 at32uc3c 4.5 exceptions and interrupts in the avr32 architecture, events are used as a common term for exceptions and interrupts. avr32uc incorporates a powerful event handling scheme. the different event sources, like ille- gal op-code and interrupt requests, have different priority levels, ensuring a well-defined behavior when multiple events are received simultaneously. additionally, pending events of a higher priority class may preempt handling of ongoing events of a lower priority class. when an event occurs, the execution of the instru ction stream is halted, and execution is passed to an event handler at an address specified in table 4-4 on page 38 . most of the handlers are placed sequentially in the code sp ace starting at the ad dress specified by evba, with four bytes between each handler. this gives ample space for a jump instruction to be placed there, jump- ing to the event routine itself. a few critical handlers have larg er spacing between them, allowing the entire event routine to be placed directly at the address specified by the evba-relative offset generated by hardware. all interrupt sources have autovectored interrupt service routine (isr) addresses. this allows the interrupt controller to directly specify the isr address as an address 90 360 mpupsr2 mpu privilege select register region 2 91 364 mpupsr3 mpu privilege select register region 3 92 368 mpupsr4 mpu privilege select register region 4 93 372 mpupsr5 mpu privilege select register region 5 94 376 mpupsr6 mpu privilege select register region 6 95 380 mpupsr7 mpu privilege select register region 7 96 384 mpucra unused in this version of avr32uc 97 388 mpucrb unused in this version of avr32uc 98 392 mpubra unused in this version of avr32uc 99 396 mpubrb unused in this version of avr32uc 100 400 mpuapra mpu access permission register a 101 404 mpuaprb mpu access permission register b 102 408 mpucr mpu control register 103 412 ss_status secure state status register 104 416 ss_adrf secure state address flash register 105 420 ss_adrr secure state address ram register 106 424 ss_adr0 secure state address 0 register 107 428 ss_adr1 secure state address 1 register 108 432 ss_sp_sys secure state stack pointer system register 109 436 ss_sp_app secure state stac k pointer application register 110 440 ss_rar secure state return address register 111 444 ss_rsr secure state return status register 112-191 448-764 reserved reserved for future use 192-255 768-1020 impl implementation defined table 4-3. system registers (continued) reg # address name function 35 32117ds?avr-01/12 at32uc3c relative to evba. the autovector offset has 14 address bits, giving an offset of maximum 16384 bytes. the target address of the event handle r is calculated as (evba | event_handler_offset), not (evba + event_handler_offse t), so evba and exception code segments must be set up appropriately. the same mechanisms are used to service all different types of events, including interrupt requests, yielding a uniform event handling scheme. an interrupt controller does the priority handling of the interrupts and provides the autovector off- set to the cpu. 4.5.1 system stack issues event handling in avr32uc uses the system stack pointed to by the system stack pointer, sp_sys, for pushing and popping r8 -r12, lr, status register, and return ad dress. since event code may be timing-critical, sp_sys should point to memory addresses in the iram section, since the timing of accesses to this memory section is both fast and deterministic. the user must also make sure that the system stack is large enough so that any event is able to push the required registers to stack. if the system stack is full, and an event occurs, the system will enter an undefined state. 4.5.2 exceptions and interrupt requests when an event other than scall or debug request is received by the core, the following actions are performed atomically: 1. the pending event will not be acce pted if it is masked. the i3 m, i2m, i1m, i0m, em, and gm bits in the status register are used to mask different events. not all events can be masked. a few critical events (nmi, unreco verable exception, tlb multiple hit, and bus error) can not be masked. when an event is accepted, hardware automatically sets the mask bits corresponding to all sources with equal or lower priority. this inhibits acceptance of other events of the same or lower priority, except for the critical events listed above. software may choose to clear some or all of these bits after saving the necessary state if other priority schemes are desired. it is the event source?s respons- ability to ensure that their events are left pending until accepted by the cpu. 2. when a request is accepted, the status register and program counter of the current context is stored to the system stack. if the event is an int0, int1, int2, or int3, reg- isters r8-r12 and lr are also automatically stored to stack. storing the status register ensures that the core is returned to the previous execution mode when the current event handling is completed. when exceptions occur, both the em and gm bits are set, and the application may manually enable nested exceptions if desired by clear- ing the appropriate bit. each exception handler has a dedicated handler address, and this address uniquely identifies the exception source. 3. the mode bits are set to reflect the priority of the accepted event, and the correct regis- ter file bank is selected. the address of the event handler, as shown in table 4-4 on page 38 , is loaded into the program counter. the execution of the event handler routine then continues from the effective address calculated. the rete instruction signals the end of the event. when encountered, the return status register and return address register are popped from the system stack and restored to the status reg- ister and program counter. if the rete instruction returns from int0, int1, int2, or int3, registers r8-r12 and lr are also popped from the system stack. the restored status register contains information allowing the core to resume operation in the previous execution mode. this concludes the event handling. 36 32117ds?avr-01/12 at32uc3c 4.5.3 supervisor calls the avr32 instruction set provides a supervisor mode call instruction. the scall instruction is designed so that privileged routines can be called from any context. this facilitates sharing of code between different execution modes. the scall mechanism is designed so that a minimal execution cycle overhead is experienced when performing supervisor routine calls from time- critical event handlers. the scall instruction behaves differently depending on which mode it is called from. the behav- iour is detailed in the instruction se t reference. in order to allow the scall routine to return to the correct context, a return from supervisor call instruction, rets , is implemented. in the avr32uc cpu, scall and rets uses the system stack to store the return address and the status register. 4.5.4 debug requests the avr32 architecture defines a dedicated debug mode. when a debug request is received by the core, debug mode is entered. entry into debug mode can be masked by the dm bit in the status register. upon entry into debug mode, hardware sets the sr.d bit and jumps to the debug exception handler. by default, debug mode executes in the exception context, but with dedicated return address register and return status register. these dedicated registers remove the need for storing this data to the system stack, t hereby improving debuggability. the mode bits in the status register can freely be manipulated in debug mode, to observe registers in all contexts, while retaining full privileges. debug mode is exited by executing the retd instruction. this return s to the previous context. 4.5.5 entry points for events several different event handler entry points exist. in avr32uc, the reset address is 0x80000000. this places the reset address in the boot flash memory area. tlb miss exceptions and scall have a dedicated space relative to evba where their event han- dler can be placed. this speeds up execution by removing the need for a jump instruction placed at the program address jumped to by the event hardware. all other exceptions have a dedicated event routine entry point located relative to evba. the handler routine address identifies the exception source directly. avr32uc uses the itlb and dtlb protection exc eptions to signal a mp u protection violation. itlb and dtlb miss exceptions are used to signal that an access address did not map to any of the entries in the mpu. tlb multiple hit exception indicates that an access address did map to multiple tlb entries, signalling an error. all interrupt requests have entry points located at an offset relative to evba. this autovector off- set is specified by an interrupt controller. the programmer must make sure that none of the autovector offsets interfere with the placement of other code. the autovector offset has 14 address bits, giving an offset of maximum 16384 bytes. special considerations should be made when loading evba with a po inter. due to security con- siderations, the event handlers should be located in non-writeable flash memory, or optionally in a privileged memory protection region if an mpu is present. if several events occur on the same instruction, they are handled in a prioritized way. the priority ordering is presented in table 4-4 on page 38 . if events occur on several instructions at different locations in the pipeline, the events on the oldest instruction are always handled before any events on any younger instruction, even if the younger instruction has events of higher priority 37 32117ds?avr-01/12 at32uc3c than the oldest instruction. an instruction b is younger than an instruction a if it was sent down the pipeline later than a. the addresses and priority of simultaneous events are shown in table 4-4 on page 38 . some of the exceptions are unused in avr32uc since it has no mmu, coprocessor interface, or floating- point unit. 38 32117ds?avr-01/12 at32uc3c table 4-4. priority and handler addresses for events priority handler address name event source stored return address 1 0x80000000 reset external input undefined 2 provided by ocd system ocd stop cpu ocd system first non-compl eted instruction 3 evba+0x00 unrecoverable exception int ernal pc of offending instruction 4 evba+0x04 tlb multiple hit mpu pc of offending instruction 5 evba+0x08 bus error data fetch data bu s first non-completed instruction 6 evba+0x0c bus error instruction fetch dat a bus first non-completed instruction 7 evba+0x10 nmi external input first non-completed instruction 8 autovectored interrupt 3 request external input first non-completed instruction 9 autovectored interrupt 2 request external input first non-completed instruction 10 autovectored interrupt 1 request external input first non-completed instruction 11 autovectored interrupt 0 request external input first non-completed instruction 12 evba+0x14 instruction address cp u pc of offending instruction 13 evba+0x50 itlb miss mpu pc of offending instruction 14 evba+0x18 itlb protection mpu pc of offending instruction 15 evba+0x1c breakpoint ocd system firs t non-completed instruction 16 evba+0x20 illegal opcode instructio n pc of offending instruction 17 evba+0x24 unimplemented instruction instr uction pc of offending instruction 18 evba+0x28 privilege violation instruc tion pc of offending instruction 19 evba+0x2c floating-point unused 20 evba+0x30 coprocessor absent instruct ion pc of offending instruction 21 evba+0x100 supervisor call instru ction pc(supervisor call) +2 22 evba+0x34 data address (read) cp u pc of offending instruction 23 evba+0x38 data address (write) cpu pc of offending instruction 24 evba+0x60 dtlb miss (read) mpu pc of offending instruction 25 evba+0x70 dtlb miss (write) mpu pc of offending instruction 26 evba+0x3c dtlb protection (read) mpu pc of offending instruction 27 evba+0x40 dtlb protection (write) m pu pc of offending instruction 28 evba+0x44 dtlb modified unused 39 32117ds?avr-01/12 at32uc3c 5. memories 5.1 embedded memories ? internal high-speed flash (see table 5-1 on page 40 ) ? 512 kbytes ? 256 kbytes ? 128 kbytes ? 64 kbytes ? 0 wait state access at up to 33 mhz in worst case conditions ? 1 wait state access at up to 66 mhz in worst case conditions ? pipelined flash architecture, allowing burst re ads from sequential fl ash locations, hiding penalty of 1 wait state access ? pipelined flash architecture typically reduces the cycle penalty of 1 wait state operation to only 15% compared to 0 wait state operation ? 100 000 write cycles, 15-year data retention capability ? sector lock capabilities, bootloader protection, security bit ? 32 fuses, erased during chip erase ? user page for data to be preserved during chip erase ? internal high-speed s ram, single-cycle access at full speed (see table 5-1 on page 40 ) ? 64 kbytes ? 32 kbytes ? 16 kbytes ? supplementary internal high-speed system sram (hsb ram), single-cycle access at full speed ? memory space available on system bus for peripherals data. ? 4 kbytes 40 32117ds?avr-01/12 at32uc3c 5.2 physical memory map the system bus is implemented as a bus matrix . all system bus addresses are fixed, and they are never remapped in any way, not even in boot. note that avr32uc cpu uses unsegmented translation, as described in the avr32 architecture manual. the 32-bit physical address space is mapped as follows: table 5-1. at32uc3c physical memory map device start address at32uc3 derivatives c0512c c1512c c2512c c0256c c1256c c2256c c0128c c1128c c2128c c064c c164c c264c embedded sram 0x0000_0000 64 kb 64 kb 64 kb 64 kb 32 kb 32 kb 16 kb 16 kb embedded flash 0x8000_0000 512 kb 512 kb 256 kb 256 kb 128 kb 128 kb 64 kb 64 kb sau 0x9000_0000 1 kb 1 kb 1 kb 1 kb 1 kb 1 kb 1 kb 1 kb hsb sram 0xa000_0000 4 kb 4 kb 4 kb 4 kb 4 kb 4 kb 4 kb 4 kb ebi sram cs0 0xc000_0000 16 mb - 16 mb - 16 mb - 16 mb - ebi sram cs2 0xc800_0000 16 mb - 16 mb - 16 mb - 16 mb - ebi sram cs3 0xcc00_0000 16 mb - 16 mb - 16 mb - 16 mb - ebi sram /sdram cs1 0xd000_0000 128 mb - 128 mb - 128 mb - 128 mb - hsb-pb bridge c 0xfffd_0000 64 kb 64 kb 64 kb 64 kb 64 kb 64 kb 64 kb 64 kb hsb-pb bridge b 0xfffe_0000 64 kb 64 kb 64 kb 64 kb 64 kb 64 kb 64 kb 64 kb hsb-pb bridge a 0xffff_0000 64 kb 64 kb 64 kb 64 kb 64 kb 64 kb 64 kb 64 kb 41 32117ds?avr-01/12 at32uc3c 5.3 peripheral address map table 5-2. flash memory parameters part number flash size (flash_pw) number of pages (flash_p) page size (flash_w) at32uc3c0512c at32uc3c1512c at32uc3c2512c 512 kbytes 1024 128 words at32uc3c0256c at32uc3c1256c at32uc3c2256c 256 kbytes 512 128 words at32uc3c0128c AT32UC3C1128C at32uc3c2128c 128 kbytes 256 128 words at32uc3c064c at32uc3c164c at32uc3c264c 64 kbytes 128 128 words table 5-3. peripheral address mapping address peripheral name 0xfffd0000 pdca peripheral dma controller - pdca 0xfffd1000 mdma memory dma - mdma 0xfffd1400 usart1 universal synchronous/asynchronous receiver/transmitter - usart1 0xfffd1800 spi0 serial peripheral interface - spi0 0xfffd1c00 canif control area network interface - canif 0xfffd2000 tc0 timer/counter - tc0 0xfffd2400 adcifa adc controller interface with touch screen functionality - adcifa 0xfffd2800 usart4 universal synchronous/asynchronous receiver/transmitter - usart4 0xfffd2c00 twim2 two-wire master interface - twim2 0xfffd3000 twis2 two-wire slave interface - twis2 42 32117ds?avr-01/12 at32uc3c 0xfffe0000 hflashc flash controller - hflashc 0xfffe1000 usbc usb 2.0 otg interface - usbc 0xfffe2000 hmatrix hsb matrix - hmatrix 0xfffe2400 sau secure access unit - sau 0xfffe2800 smc static memory controller - smc 0xfffe2c00 sdramc sdram controller - sdramc 0xfffe3000 macb ethernet mac - macb 0xffff0000 intc interrupt controller - intc 0xffff0400 pm power manager - pm 0xffff0800 scif system control interface - scif 0xffff0c00 ast asynchronous timer - ast 0xffff1000 wdt watchdog timer - wdt 0xffff1400 eic external interrupt controller - eic 0xffff1800 freqm frequency meter - freqm 0xffff2000 gpio general purpose input/ output controller - gpio 0xffff2800 usart0 universal synchronous/asynchronous receiver/transmitter - usart0 0xffff2c00 usart2 universal synchronous/asynchronous receiver/transmitter - usart2 0xffff3000 usart3 universal synchronous/asynchronous receiver/transmitter - usart3 0xffff3400 spi1 serial peripheral interface - spi1 table 5-3. peripheral address mapping 43 32117ds?avr-01/12 at32uc3c 5.4 cpu local bus mapping some of the registers in the gpio module are mapped onto the cpu local bus, in addition to being mapped on the peripheral bus. these registers can therefore be reached both by accesses on the peripheral bus, and by accesses on the local bus. mapping these registers on the local bus allows cycle-deterministic toggling of gpio pins since the cpu and gpio are the only modules connected to this bus. also, since the local bus runs at cpu speed, one write or read operation can be pe rformed per clock cycle to the local bus- mapped gpio registers. 0xffff3800 twim0 two-wire master interface - twim0 0xffff3c00 twim1 two-wire master interface - twim1 0xffff4000 twis0 two-wire slave interface - twis0 0xffff4400 twis1 two-wire slave interface - twis1 0xffff4800 iisc inter-ic sound (i 2s) controller - iisc 0xffff4c00 pwm pulse width modulation controller - pwm 0xffff5000 qdec0 quadrature decoder - qdec0 0xffff5400 qdec1 quadrature decoder - qdec1 0xffff5800 tc1 timer/counter - tc1 0xffff5c00 pevc peripheral event controller - pevc 0xffff6000 acifa0 analog comparators interface - acifa0 0xffff6400 acifa1 analog comparators interface - acifa1 0xffff6800 dacifb0 dac interface - dacifb0 0xffff6c00 dacifb1 dac interface - dacifb1 0xffff7000 aw awire - aw table 5-3. peripheral address mapping 44 32117ds?avr-01/12 at32uc3c the following gpio registers are mapped on the local bus: table 5-4. local bus mapped gpio registers port register mode local bus address access a output driver enable register (oder) write 0x40000040 write-only set 0x40000044 write-only clear 0x40000048 write-only toggle 0x4000004c write-only output value register (ovr) write 0x40000050 write-only set 0x40000054 write-only clear 0x40000058 write-only toggle 0x4000005c write-only pin value register (pvr) - 0x40000060 read-only b output driver enable register (oder) write 0x40000140 write-only set 0x40000144 write-only clear 0x40000148 write-only toggle 0x4000014c write-only output value register (ovr) write 0x40000150 write-only set 0x40000154 write-only clear 0x40000158 write-only toggle 0x4000015c write-only pin value register (pvr) - 0x40000160 read-only c output driver enable register (oder) write 0x40000240 write-only set 0x40000244 write-only clear 0x40000248 write-only toggle 0x4000024c write-only output value register (ovr) write 0x40000250 write-only set 0x40000254 write-only clear 0x40000258 write-only toggle 0x4000025c write-only pin value register (pvr) - 0x40000260 read-only 45 32117ds?avr-01/12 at32uc3c d output driver enable register (oder) write 0x40000340 write-only set 0x40000344 write-only clear 0x40000348 write-only toggle 0x4000034c write-only output value register (ovr) write 0x40000350 write-only set 0x40000354 write-only clear 0x40000358 write-only toggle 0x4000035c write-only pin value register (pvr) - 0x40000360 read-only table 5-4. local bus mapped gpio registers port register mode local bus address access 46 32117ds?avr-01/12 at32uc3c 6. supply and startup considerations 6.1 supply considerations 6.1.1 power supplies the at32uc3c has several types of power supply pins: ? vddio pins (vddio1, vddio2, vddio3): power i/o lines. two voltage ranges are available: 5v or 3.3v nominal. the vddio pins should be connected together. ? vddana: powers the analog part of the device (analog i/os, adc, acs, dacs). 2 voltage ranges available: 5v or 3.3v nominal. ? vddin_5: input voltage for the 1.8v and 3.3v regu lators. two voltage ranges are available: 5v or 3.3v nominal. ? vddin_33: ? usb i/o power supply ? if the device is 3.3v powered: input voltage, voltage is 3.3v nominal. ? if the device is 5v powered: stabilization for the 3.3v voltage regulator, requires external capacitors ? vddcore: stabilization for the 1.8v voltag e regulator, requires external capacitors. ? gndcore: ground pins for the vo ltage regulators and the core. ? gndana: ground pin for an alog part of the design ? gndpll: ground pin for the plls ? gndio pins (gndio1, gndio2, gndio3): ground pins for the i/o lines. the gndio pins should be connected together. see ?electrical characteristics? on page 50 for power consumption on the various supply pins. for decoupling recommendations for the different power supplies, please refer to the schematic checklist. 6.1.2 voltage regulators the at32uc3c embeds two voltage regulators: ? one 1.8v internal regulator that converts from vddin_5 to 1.8v. the regulator supplies the output voltage on vddcore. ? one 3.3v internal regulator that converts from vddin_5 to 3.3v. the regulator supplies the usb pads on vddin_33. if the usb is not used or if vddin_5 is within the 3v range, the 3.3v regulator can be disabled through the vreg33ctl field of the vregctrl scif register. 6.1.3 regulators connection the at32uc3c supports two power supply configurations. ? 5v single supply mode ? 3.3v single supply mode 6.1.3.1 5v single supply mode in 5v single supply mode, the 1.8v internal regulator is connected to the 5v source (vddin_5 pin) and its output feeds vddcore. 47 32117ds?avr-01/12 at32uc3c the 3.3v regulator is connected to the 5v sour ce (vddin_5 pin) and its output feeds the usb pads. if the usb is not used, the 3.3v regulator can be disabled through the vreg33ctl field of the vregctrl scif register. figure 6-1 on page 47 shows the power schematics to be used for 5v single supply mode. all i/o lines and analog blocks will be powered by the same power (vddin_5 = vddio1 = vddio2 = vddio3 = vddana). figure 6-1. 5v single power supply mode 6.1.3.2 3.3v single supply mode in 3.3v single supply mode, the vddin_5 and vddin_33 pins should be connected together externally. the 1.8v internal regulator is connected to the 3.3v source (vddin_5 pin) and its output feeds vddcore. the 3.3v regulator should be disabled once the circuit is running through the vreg33ctl field of the vregctrl scif register. figure 6-2 on page 48 shows the power schematics to be used for 3.3v single supply mode. all i/o lines and analog blocks will be powered by the same power (vddin_5 = vddin_33 = vddio1 = vddio2 = vddio3 = vddana). vddio1 vddio2 vddio3 cpu peripherals memories scif, bod, rcsys 3.3v reg + - analog: adc, ac, dac, ... vddin_5 vddana gndana vddcore c out2 c out1 gndcore gndpll pll gndio1 gndio2 gndio3 bod50 bod18 bod33 1.8v reg por c in2 c in1 vddin_33 c out2 c out1 4.5- 5.5v 48 32117ds?avr-01/12 at32uc3c figure 6-2. 3 single power supply mode 6.1.4 power-up sequence 6.1.4.1 maximum rise rate to avoid risk of latch-up, the rise rate of the power supplies must not exceed the values described in table 7-2 on page 51 . recommended order for power supplies is also described in this table. 6.1.4.2 minimum rise rate the integrated power-reset circuitry monitori ng the powering supply requires a minimum rise rate for the vddin_5 power supply. see table 7-2 on page 51 for the minimum rise rate value. if the application can not ensure that the minimum rise rate condition for the vddin power sup- ply is met, the following configuration can be used: ? a logic ?0? value is applied durin g power-up on pin reset_n until: ? vddin_5 rises above 4.5v in 5v single supply mode. ? vddin_33 rises above 3v in 3.3v single supply mode. vddin_33 cpu peripherals memories scif, bod, rcsys 3.3v reg analog: adc, ac, dac, ... vddin_5 vddana gndana vddcore c out2 c out1 gndcore gndpll pll bod50 bod33 1.8v reg bod18 por + - 3.0- 3.6v c in2 c in1 vddio1 vddio2 vddio3 gndio1 gndio2 gndio3 49 32117ds?avr-01/12 at32uc3c 6.2 startup considerations this chapter summarizes the boot sequence of the at32uc3c. the behavior after power-up is controlled by the power manager. for specific details, refer to the power manager chapter. 6.2.1 starting of clocks at power-up, the bod33 and the bod18 are enabled. the device w ill be held in a reset state by the power-up circuitry, until the vddin_33 (resp. vddcore) has reached the reset threshold of the bod33 (resp bod18). refer to the electrical characteristics for the bod thresholds. once the power has stabilized, the device will use the system rc oscillator (rcsys, 115khz typical frequency) as clock source. the bod18 and bod33 are kept enabled or are disabled according to the fuse settings (see the fuse setting section in the flash controller chapter). on system start-up, the plls are disabled. all clocks to all modules are running. no clocks have a divided frequency, all parts of the system receive a clock with the same frequency as the inter- nal rc oscillator. 6.2.2 fetching of initial instructions after reset has been released, the avr32uc cpu st arts fetching instructions from the reset address, which is 0x8000_0000. this address points to the first address in the internal flash. the internal flash uses vddio voltage during read and write operations. it is recommended to use the bod33 to monitor this voltage and make sure the vddio is above the minimum level (3.0v). the code read from the internal flash is free to configure the system to use for example the plls, to divide the frequency of the clock routed to some of the peripherals, and to gate the clocks to unused peripherals. 50 32117ds?avr-01/12 at32uc3c 7. electrical characteristics 7.1 absolute maximum ratings* notes: 1. v vdd corresponds to either v vddio1 , v vddio2 , v vddio3 , or v vddana , depending on the supply for the pin. refer to section 3-1 on page 11 for details. 7.2 supply characteristics the following characteristics are applicable to the operating temperature range: t a = -40c to 85c, unless otherwise spec- ified and are valid for a junction temperature up to t j = 100c. please refer to section 6. ?supply and startup considerations? on page 46 . operating temperature..................................... -40c to +85c *notice: stresses beyond those listed under ?absolute maximum ratings? may cause permanent dam- age to the device. this is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of th is specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. storage temperature...................................... -60c to +150c voltage on any pin except dm/dp/vbus with respect to ground ............................ -0.3v to v vdd (1) +0.3v voltage on dm/dp with respect to ground.........-0.3v to +3.6v voltage on vbus with respect to ground...........-0.3v to +5.5v maximum operating voltage (vddin_5) ........................... 5.5v maximum operating voltage (vddio1, vddio2, vddio3, vddana).......................................................................... 5.5v maximum operating voltage (vdd in_33) ............ ............. 3.6v total dc output current on all i/o pins- vddio1 ......... 120 ma total dc output current on all i/o pins- vddio2 ......... 120 ma total dc output current on all i/o pins- vddio3 ......... 120 ma total dc output current on all i/o pins- vddana........ 120 ma table 7-1. supply characteristics symbol parameter condition voltage min max unit v vddin_5 dc supply internal regulators 3v range 3.0 3.6 v 5v range 4.5 5.5 v vddin_33 dc supply usb i/o only in 3v range 3.0 3.6 v v vddana dc supply peripheral i/o and analog part 3v range 3.0 3.6 v 5v range 4.5 5.5 v vddio1 v vddio2 v vddio2 dc supply peripheral i/o 3v range 3.0 3.6 v 5v range 4.5 5.5 51 32117ds?avr-01/12 at32uc3c 7.3 maximum clock frequencies these parameters are given in the following conditions: ?v vddcore > 1.85v ? temperature = -40c to 85c note: 1. these values are based on simulation and characterization of other avr microcontrollers manufactured in the same pro- cess technology. these values are not covered by test limits in production. 7.4 power consumption the values in table 7-4 are measured values of power consumption under the following condi- tions, except where noted: ? operating conditions core supply ( figure 7-1 ) ?v vddin_5 = v vddin_33 = 3.3v ?v vddcore = 1.85v, supplied by the internal regulator ?v vddio1 = v vddio2 = v vddio3 = 3.3v ?v vddana = 3.3v table 7-2. supply rise rates and order symbol parameter rise rate min max comment v vddin_5 dc supply internal 3.3v regulator 0.01 v/ms 1.25 v/us v vddin_33 dc supply internal 1.8v regulator 0.01 v/ms 1.25 v/us v vddio1 v vddio2 v vddio3 dc supply peripheral i/o 0.01 v/ms 1.25 v/us rise after or at the same time as vddin_5, vddin_33 v vddana dc supply peripheral i/o and analog part 0.01 v/ms 1.25 v/us rise after or at the same time as vddin_5, vddin_33 table 7-3. clock frequencies symbol parameter conditions min max units f cpu cpu clock frequency 66 mhz f pba pba clock frequency 66 mhz f pbb pbb clock frequency 66 mhz f pbc pbc clock frequency 66 mhz f gclk0 gclk0 clock frequency generic clock for usbc 50 (1) mhz f gclk1 gclk1 clock frequency generic clock for canif 66 (1) mhz f gclk2 gclk2 clock frequency generic clock for ast 80 (1) mhz f gclk4 gclk4 clock frequency generic clock for pwm 133 (1) mhz f gclk11 gclk11 clock frequency generic clock for iisc 50 (1) mhz 52 32117ds?avr-01/12 at32uc3c ? internal 3.3v regulator is off ?t a = 25 c ? i/os are configured as inputs, with internal pull-up enabled. ? oscillators ? osc0/1 (crystal oscillator) stopped ? osc32k (32khz crystal oscillator) stopped ? pll0 running ? pll1 stopped ? clocks ? external clock on xin0 as main clock source ( 10mhz ) ? cpu, hsb, and pbb clocks undivided ? pba, pbc clock divided by 4 ? all peripheral clocks running note: 1. these numbers are valid for the measured condition only and must not be extrapolated to other frequencies. table 7-4. power consumption for different operating modes mode conditions measured on consumption typ unit active (1) cpu running a recursive fibonacci algorithm amp 512 a/mhz idle (1) 258 frozen (1) 106 standby (1) 48 stop 73 a deepstop 43 static osc32k and ast running 32 ast and osc32k stopped 31 53 32117ds?avr-01/12 at32uc3c figure 7-1. measurement schematic 7.4.1 peripheral power consumption the values in table 7-5 are measured values of power consumption under the following conditions. ? operating conditions core supply ( figure 7-1 ) ?v vddin_5 = v ddin_33 = 3.3v ?v vddcore = 1.85v , supplied by the internal regulator ?v vddio1 = v vddio2 = v vddio3 = 3.3v ?v vddana = 3.3v ? internal 3.3v regulator is off. ?t a = 25 c ? i/os are configured as inputs, with internal pull-up enabled. ? oscillators ? osc0/1 (crystal oscillator) stopped ? osc32k (32khz crystal oscillator) stopped ? pll0 running amp vddana vddio vddin_5 vddcore gndcore gndpll vddin_33 54 32117ds?avr-01/12 at32uc3c ? pll1 stopped ? clocks ? external clock on xin0 as main clock source. ? cpu, hsb, and pb clocks undivided consumption active is the added current cons umption when the module clock is turned on and when the module is doing a typical set of operations. notes: 1. includes the current consumption on vddana. 2. these numbers are valid for the measured condi tion only and must not be extrapolated to other frequencies. table 7-5. typical current consumption by peripheral (2) peripheral typ consumption active unit acifa (1) 3 a/mhz adcifa (1) 7 ast 3 canif 25 dacifb (1) 3 ebi 23 eic 0.5 freqm 0.5 gpio 37 intc 3 mdma 4 pdca 24 pevc 15 pwm 40 qdec 3 sau 3 sdramc 2 smc 9 spi 5 tc 8 twim 2 twis 2 usart 10 usbc 5 wdt 2 55 32117ds?avr-01/12 at32uc3c 7.5 i/o pin c haracteristics table 7-6. normal i/o pin characteristics (1) symbol parameter condi tion min typ max units r pullup pull-up resistance v vdd = 3v 5 26 kohm v vdd = 5v 5 16 kohm r pulldown pull-down resistance 2 16 kohm v il input low-level voltage v vdd = 3v 0.3*v vddio v v vdd = 4.5v 0.3*v vddio v ih input high-level voltage v vdd = 3.6v 0.7*v vddio v v vdd = 5.5v 0.7*v vddio v ol output low-level voltage i ol = -3.5ma, pin drive x1 (2) 0.45 v i ol = -7ma, pin drive x2 (2) i ol = -14ma, pin drive x4 (2) v oh output high-level voltage i oh = 3.5ma, pin drive x1 (2) v vdd - 0.8 v i oh = 7ma, pin drive x2 (2) i oh = 14ma, pin drive x4 (2) f max output frequency (3) v vdd = 3.0v load = 10pf, pin drive x1 (2) 35 mhz load = 10pf, pin drive x2 (2) 55 load = 10pf, pin drive x4 (2) 70 load = 30pf, pin drive x1 (2) 15 load = 30pf, pin drive x2 (2) 30 load = 30pf, pin drive x4 (2) 45 v vdd =4.5v load = 10pf, pin drive x1 (2) 50 load = 10pf, pin drive x2 (2) 80 load = 10pf, pin drive x4 (2) 95 load = 30pf, pin drive x1 (2) 25 load = 30pf, pin drive x2 (2) 40 load = 30pf, pin drive x4 (2) 65 56 32117ds?avr-01/12 at32uc3c note: 1. v vdd corresponds to either v vddio1 , v vddio2 , v vddio3 , or v vddana , depending on the supply for the pin. refer to section 3-1 on page 11 for details. 2. drive x1 capability pins are: pb00, pb01, pb02, pb03, pb 30, pb31, pc02, pc03, pc04, pc05, pc06, pc07 - drive x2 /x4 capability pins are: pb06, pb21, pb26, pd02, pd06, pd13 - drive x1/x2 capability pins are the remaining pa, pb, pc, pd pins. the drive strength is programmable through odcr0, odcr0s, odcr0c, odcr0t registers of gpio. 3. these values are based on simulation and characterization of other avr microcontrollers manufactured in the same pro- cess technology. these values are not covered by test limits in production. t rise rise time (3) v vdd = 3.0v load = 10pf, pin drive x1 (2) 7.7 ns load = 10pf, pin drive x2 (2) 3.4 load = 10pf, pin drive x4 (2) 1.9 load = 30pf, pin drive x1 (2) 16 load = 30pf, pin drive x2 (2) 7.5 load = 30pf, pin drive x4 (2) 3.8 v vdd = 4.5v load = 10pf, pin drive x1 (2) 5.3 load = 10pf, pin drive x2 (2) 2.4 load = 10pf, pin drive x4 (2) 1.3 load = 30pf, pin drive x1 (2) 11.1 load = 30pf, pin drive x2 (2) 5.2 load = 30pf, pin drive x4 (2) 2.7 t fall fall time (3) v vdd = 3.0v load = 10pf, pin drive x1 (2) 7.6 ns load = 10pf, pin drive x2 (2) 3.5 load = 10pf, pin drive x4 (2) 1.9 load = 30pf, pin drive x1 (2) 15.8 load = 30pf, pin drive x2 (2) 7.3 load = 30pf, pin drive x4 (2) 3.8 v vdd = 4.5v load = 10pf, pin drive x1 (2) 5.2 load = 10pf, pin drive x2 (2) 2.4 load = 10pf, pin drive x4 (2) 1.4 load = 30pf, pin drive x1 (2) 10.9 load = 30pf, pin drive x2 (2) 5.1 load = 30pf, pin drive x4 (2) 2.7 i leak input leakage current pull-up resistors disabled 1.0 a c in input capacitance pa00-pa29, pb00-pb31, pc00-pc01, pc08-pc31, pd00-pd30 7.5 pf pc02, pc03, pc04, pc05, pc06, pc07 2 table 7-6. normal i/o pin characteristics (1) symbol parameter condi tion min typ max units 57 32117ds?avr-01/12 at32uc3c 7.6 oscillator characteristics 7.6.1 oscillator (osc0 and osc1) characteristics 7.6.1.1 digital clock characteristics the following table describes the characteristics for the oscillator when a digital clock is applied on xin0 or xin1. 7.6.1.2 crystal oscilla tor characteristics the following table describes the characteristics for the oscillator when a crystal is connected between xin and xout as shown in figure 7-2 . the user must choose a crystal oscillator where the crystal load capacitance c l is within the range given in the table. the exact value of c l can be found in the crystal datasheet. the capacitance of the external capacitors (c lext ) can then be computed as follows: where c pcb is the capacitance of the pcb and c i is the internal equivalent load capacitance. figure 7-2. oscillator connection table 7-7. digital clock ch aracteristics symbol parameter conditions min typ max units f cpxin xin clock frequency 50 mhz t cpxin xin clock period 20 ns t chxin xin clock high half-priod 0.4 x t cpxin 0.6 x t cpxin ns t clxin xin clock low half-priod 0.4 x t cpxin 0.6 x t cpxin ns c in xin input capacitance 2 pf c lext 2c l c i ? () c pcb ? = xin xout c lext c lext c i c l uc3c 58 32117ds?avr-01/12 at32uc3c notes: 1. please refer to th e scif chapter for details. 7.6.2 32khz crystal oscillator (osc32k) characteristics 7.6.2.1 digital clock characteristics the following table describes the characteristics for the oscillator when a digital clock is applied on xin32. 7.6.2.2 crystal oscilla tor characteristics figure 7-2 and the equation above also applies to the 32khz oscillator connection. the user must choose a crystal oscillator where the crystal load capacitance c l is within the range given in the table. the exact value of c l can then be found in the crystal datasheet.. table 7-8. crystal oscillator characteristics symbol parameter conditions min typ max unit f out crystal oscillator frequency 0.4 20 mhz c i internal equivalent load capacitance 1.7 pf t startup startup time f out = 8mhz scif.oscctrl.gain = 1 (1) 975 us f out = 16mhz scif.oscctrl.gain = 2 (1) 1100 us table 7-9. digital 32khz clock characteristics symbol parameter conditions min typ max units f cpxin xin32 clock frequency 32.768 5000 khz t cpxin xin32 clock period 200 ns t chxin xin32 clock high half-priod 0.4 x t cpxin 0.6 x t cpxin ns t clxin xin32 clock low half-priod 0.4 x t cpxin 0.6 x t cpxin ns c in xin32 input capacitance 2 pf table 7-10. 32 khz crystal oscillator characteristics symbol parameter conditions min typ max unit f out crystal oscillator frequency 32 768 hz t startup startup time r s = 50 kohm, c l = 12.5pf 2 s c l crystal load capacitance 6 15 pf c i internal equivalent load capacitance 1.4 pf 59 32117ds?avr-01/12 at32uc3c 7.6.3 phase lock loop (pll0 and pll1) characteristics 7.6.4 120mhz rc oscillator (rc120m) characteristics note: 1. these values are based on simulation and characterization of other avr microcontrollers manufactured in the same pro- cess technology. these values are not covered by test limits in production. 7.6.5 system rc oscillator (rcsys) characteristics 7.6.6 8mhz/1mhz rc oscillator (rc8m) characteristics notes: 1. please refer to th e scif chapter for details. table 7-11. pll characteristics symbol parameter conditions min typ max unit f vco output frequency 80 240 mhz f in input frequency 4 16 mhz i pll current consumption active mode, f vco = 80mhz 250 a active mode, f vco = 240mhz 600 t startup startup time, from enabling the pll until the pll is locked wide bandwidth mode disabled 15 s wide bandwidth mode enabled 45 table 7-12. internal 120mhz rc oscillator characteristics symbol parameter conditions min typ max unit f out output frequency (1) 88 120 152 mhz i rc120m current consumption 1.85 ma t startup startup time 3s table 7-13. system rc oscillator characteristics symbol parameter conditions min typ max unit f out output frequency calibrated at t a = 85c 110 115.2 120 khz t a = 25c 105 109 115 t a = -40c 100 104 108 table 7-14. 8mhz/1mhz rc oscilla tor characteristics symbol parameter conditions min typ max unit f out output frequency scif.rccr8.freqmode = 0 (1) 7.6 8 8.4 mhz scif.rccr8.freqmode = 1 (1) 0.955 1 1.045 t startup startup time 20 s 60 32117ds?avr-01/12 at32uc3c 7.7 flash characteristics table 7-15 gives the device maximum operating frequency depending on the number of flash wait states. the fsw bit in the flashc fsr regist er controls the number of wait states used when accessing the flash memory. table 7-15. maximum operating frequency flash wait states read mode maximum operating frequency 0 1 cycle 33mhz 1 2 cycles 66mhz table 7-16. flash characteristics symbol parameter conditions min typ max unit t fpp page programming time f clk_hsb = 66mhz 4.3 ms t fpe page erase time 4.3 t ffp fuse programming time 0.6 t fea full chip erase time (ea) 4.9 t fce jtag chip erase time (chip_erase) f clk_hsb = 115khz 640 table 7-17. flash endurance and data retention symbol parameter condit ions min typ max unit n farray array endurance (write/page) 100k cycles n ffuse general purpose fuses endu rance (write/bit) 1k cycles t ret data retention 15 years 61 32117ds?avr-01/12 at32uc3c 7.8 analog characteristics 7.8.1 1.8v voltage regulator characteristics 7.8.2 3.3v voltage regulator characteristics 7.8.3 1.8v brown out detector (bod18) characteristics the values in table 7-21 describe the values of the bo d.level in the scif module. table 7-18. 1.8v voltage regulator electrical characteristics symbol parameter condition min typ max units v vddin_5 input voltage range 5v range 4.5 5.5 v 3v range 3.0 3.6 v vddcore output voltage, calibrated value 1.85 v i out dc output current 80 ma table 7-19. decoupling requirements symbol parameter condition typ techno. units c in1 input regulator capacitor 1 1 npo nf c in2 input regulator capacitor 2 4.7 x7r uf c out1 output regulator capacitor 1 470 npo pf c out2 output regulator capacitor 2 2.2 x7r uf table 7-20. 3.3v voltage regulator electrical characteristics symbol parameter condition min typ max units v vddin_5 input voltage range 4.5 5.5 v v vddin_33 output voltage, calibrated value 3.4 v i out dc output current 35 ma i vreg static current of regulator low power mode 10 a table 7-21. bodlevel values bodlevel value param eter min max units 0 1.29 1.58 v 20 1.36 1.63 26 threshold at power-up sequence 1.42 1.69 28 1.43 1.72 32 1.48 1.77 36 1.53 1.82 40 1.56 1.88 62 32117ds?avr-01/12 at32uc3c 7.8.4 3.3v brown out detector (bod33) characteristics the values in table 7-23 describe the values of the bod33.level field in the scif module. 7.8.5 5v brown out detector (bod50) characteristics the values in table 7-25 describe the values of the bod50.level field in the scif module. table 7-23. bod33.level values bod33.level value par ameter min max units 17 2.21 2.55 v 22 2.30 2.64 27 2.39 2.74 31 threshold at power-up sequence 2.46 2.82 33 2.50 2.86 39 2.60 2.98 44 2.69 3.08 49 2.78 3.18 53 2.85 3.27 60 2.98 3.41 table 7-25. bod50.level values bod50.level value par ameter min max units 16 3.20 3.65 v 25 3.42 3.92 35 3.68 4.22 44 3.91 4.48 53 4.15 4.74 61 4.36 4.97 63 32117ds?avr-01/12 at32uc3c 7.8.6 analog to digital converter (adc) a nd sample and hold (s/h) characteristics table 7-27. adc and s/h characteristics symbol parameter conditions min typ max units f adc adc clock frequency 12-bit resolution mode, v vddana = 3v 1.2 mhz 10-bit resolution mode, v vddana = 3v 1.6 8-bit resolution mode, v vddana = 3v 2.2 12-bit resolution mode, v vddana = 4.5v 1.5 10-bit resolution mode, v vddana = 4.5v 2 8-bit resolution mode, v vddana = 4.5v 2.4 t startup startup time adc cold start-up 1 ms adc hot start-up 24 adc clock cycles t conv conversion time (latency) (adcifa.seqcfgn.sres)/2 + 2, adcifa.cfg.shd = 1 68 adc clock cycles (adcifa.seqcfgn.sres)/2 + 3, adcifa.cfg.shd = 0 79 throughput rate 12-bit resolution, adc clock = 1.2 mhz, v vddana = 3v 1.2 msps 10-bit resolution, adc clock = 1.6 mhz, v vddana = 3v 1.6 12-bit resolution, adc clock = 1.5 mhz, v vddana = 4.5v 1.5 10-bit resolution, adc clock = 2 mhz, v vddana = 4.5v 2 table 7-28. adc reference voltage symbol parameter conditions min typ max unit s v adcref0 adcref0 input voltage range 5v range 1 3.5 v 3v range 1 v vddana -0.7 v adcref1 adcref1 input voltage range 5v range 1 3.5 v 3v range 1 v vddana -0.7 v adcrefp adcrefp input voltage 5v range - voltage reference applied on adcrefp 13.5 v 3v range - voltage reference applied on adcrefp 1v vddana -0.7 v adcrefn adcrefn input voltage voltage reference applied on adcrefn gndana v internal 1v reference 1.0 v internal 0.6*vddana reference 0.6*v vddana v 64 32117ds?avr-01/12 at32uc3c figure 7-3. adc input table 7-29. adc decoupling requirements symbol parameter conditions min typ max units c adcrefpn adcrefp/adcrefn capacitance no voltage reference appplied on adcrefp/adcrefn 100 nf table 7-30. adc inputs symbol parameter conditions min typ max units v adcinn adc input voltage range 0 v vddana v c onchip internal capacitance adc used without s/h 5 pf adc used with s/h 4 r onchip switch resistance adc used without s/h 5.1 k adc used with s/h 4.6 c source v in r source adcin r onchip uc3c c onchip table 7-31. adc transfer characteristics 12-bit resolution mode (1) symbol parameter conditions min typ max units res resolution differential mode, v vddana = 3v, v adcref0 = 1v, adcfia.seqcfgn.sres = 0 (f adc = 1.2mhz) 12 bit inl integral non-linearity 5lsb dnl differential non-linearity 3 lsb offset error -7 7 mv gain error -20 20 mv 65 32117ds?avr-01/12 at32uc3c note: 1. the measures are done without any i/o activity on vddana/gndana power domain. note: 1. the measures are done without any i/o activity on vddana/gndana power domain. note: 1. the measures are done without any i/o activity on vddana/gndana power domain. res resolution differential mode, v vddana = 5v, v adcref0 = 3v, adcfia.seqcfgn.sres = 0 (f adc = 1.5mhz) 12 bit inl integral non-linearity 4lsb dnl differential non-linearity 3 lsb offset error -15 15 mv gain error -25 25 mv table 7-31. adc transfer characteristics (continued)12-bit resolution mode (1) symbol parameter conditions min typ max units table 7-32. adc transfer characteristics 10-bit resolution mode (1) symbol parameter conditions min typ max units res resolution differential mode, v vddana = 3v, v adcref0 = 1v, adcfia.seqcfgn.sres = 1 (f adc = 1.5mhz) 10 bit inl integral non-linearity 1.25 lsb dnl differential non-linearity 1lsb offset error -10 10 mv gain error -20 20 mv res resolution differential mode, v vddana = 5v, v adcref0 = 3v, adcfia.seqcfgn.sres = 1 (f adc = 1.5mhz) 10 bit inl integral non-linearity 1.25 lsb dnl differential non-linearity 1lsb offset error -15 15 mv gain error -20 20 mv table 7-33. adc transfer characteristics 8-bit resolution mode (1) symbol parameter conditions min typ max units res resolution differential mode, v vddana = 3v, v adcref0 = 1v, adcfia.seqcfgn.sres = 2 (f adc =1.5mhz) 8bit inl integral non-linearity 0.3 lsb dnl differential non-linearity 0.25 lsb offset error -10 10 mv gain error -20 20 mv res resolution differential mode, v vddana = 5v, v adcref0 = 3v, adcfia.seqcfgn.sres = 2 (f adc = 1.5mhz) 8bit inl integral non-linearity 0.2 lsb dnl differential non-linearity 0.2 lsb offset error -20 20 mv gain error -20 20 mv 66 32117ds?avr-01/12 at32uc3c note: 1. the measures are done without any i/o activity on vddana/gndana power domain. note: 1. the measures are done without any i/o activity on vddana/gndana power domain table 7-34. adc and s/h transfer characteristics 12-bit resolution mode and s/h gain = 1 (1) symbol parameter conditions min typ max units res resolution differential mode, v vddana = 3v, v adcref0 = 1v, adcfia.seqcfgn.sres = 0, s/h gain = 1 (f adc = 1.2mhz) 12 bit inl integral non-linearity 5lsb dnl differential non-linearity 4lsb offset error -5 5 mv gain error -20 20 mv res resolution differential mode, v vddana = 5v, v adcref0 = 3v, adcfia.seqcfgn.sres = 0, s/h gain = 1 (f adc = 1.5mhz) 12 bit inl integral non-linearity 5lsb dnl differential non-linearity 3lsb offset error -10 10 mv gain error -20 20 mv table 7-35. adc and s/h transfer characteristics 12-bit resolution mode and s/h gain from 1 to 8 (1) symbol parameter conditions min typ max units res resolution differential mode, v vddana = 3v, v adcref0 = 1v, adcfia.seqcfgn.sres = 0, s/h gain from 1 to 8 (f adc = 1.2mhz) 12 bit inl integral non-linearity 25 lsb dnl differential non-linearity 25 lsb offset error -10 10 mv gain error -20 20 mv res resolution differential mode, v vddana = 5v, v adcref0 = 3v, adcfia.seqcfgn.sres = 0, s/h gain from 1 to 8 (f adc = 1.5mhz) 12 bit inl integral non-linearity 9lsb dnl differential non-linearity 10 lsb offset error -15 15 mv gain error -20 20 mv table 7-36. adc and s/h transfer characteristics 10-bit resolution mode and s/h gain from 1 to 16 (1) symbol parameter conditions min typ max units res resolution differential mode, v vddana = 3v, v adcref0 = 1v, adcfia.seqcfgn.sres = 1, s/h gain from 1 to 16 (f adc = 1.5mhz) 10 bit inl integral non-linearity 3lsb dnl differential non-linearity 3lsb offset error -15 15 mv gain error -20 20 mv 67 32117ds?avr-01/12 at32uc3c note: 1. the measures are done without any i/o activity on vddana/gndana power domain. 7.8.7 digital to analog converter (dac) characteristics res resolution differential mode, v vddana = 5v, v adcref0 = 3v, adcfia.seqcfgn.sres = 1, s/h gain from 1 to 16 (f adc = 1.5mhz) 10 bit inl integral non-linearity 1.5 lsb dnl differential non-linearity 1.5 lsb offset error -25 25 mv gain error -15 15 mv table 7-36. adc and s/h transfer characteristics (continued)10-bit resolution mode and s/h gain from 1 to 16 (1) symbol parameter conditions min typ max units table 7-37. channel conversion time and dac clock symbol parameter conditions min typ max units f dac dac clock frequency 1mhz t startup startup time 3s t conv conversion time (latency) no s/h enabled, internal dac 1 s one s/h 1.5 s tw o s / h 2 s throughput rate 1/t conv msps table 7-38. external voltage reference input symbol parameter conditions min typ max units v dacref dacref input voltage range 1.2 v vddana -0.7 v table 7-39. dac outputs symbol parameter conditions min typ max units output range with external dac reference 0.2 v dacref v with internal dac reference 0.2 v vddana -0.7 c load output capacitance 0 100 pf r load output resitance 2 k 68 32117ds?avr-01/12 at32uc3c figure 7-4. dac output note: 1. the measures are done without any i/o activity on vddana/gndana power domain. c load r load dac0a uc3c s/h dac table 7-40. transfer characteristics (1) symbol parameter conditions min typ max units res resolution v vddana = 3v, v dacref = 2v, one s/h 12 bit inl integral non-linearity 8 lsb dnl differential non-linearity 6 lsb offset error -30 30 mv gain error -30 30 mv res resolution v vddana = 5v, v dacref = 3v, one s/h 12 bit inl integral non-linearity 12 lsb dnl differential non-linearity 6 lsb offset error -30 30 mv gain error -30 30 mv 69 32117ds?avr-01/12 at32uc3c 7.8.8 analog comparator characteristics note: 1. the measures are done without any i/o activity on vddana/gndana power domain. 7.8.9 usb transceiver characteristics 7.8.9.1 electrical characteristics the usb on-chip buffers comply with the univ ersal serial bus (usb) v2.0 standard. all ac parameters related to these buffers can be foun d within the usb 2.0 electrical specifications. table 7-41. analog comparator characteristics (1) symbol parameter conditions min typ max units positive input voltage range 0 v vddana v negative input voltage range 0 v vddana v v offset offset no hysteresis, low power mode -29 29 mv no hysteresis, high speed mode -16 16 mv v hyst hysteresis low hysteresis, low power mode 7 44 mv low hysteresis, high speed mode 5 34 high hysteresis, low power mode 16 102 mv high hysteresis, high speed mode 12 69 t delay propagation delay low power mode 2.9 us high speed mode 0.096 t startup start-up time 20 s table 7-42. vddana scaled reference symbol parameter min typ max units scf acifa.scfi.scf range 0 32 v vddana scaled (64 - scf) * v vddana / 65 v v vddana voltage accuracy 3.2 % table 7-43. electrical parameters symbol parameter conditions min. typ. max. unit r ext recommended external usb series resistor in series with each usb pin with 5% 39 70 32117ds?avr-01/12 at32uc3c 7.9 timing characteristics 7.9.1 startup, reset, and wake-up timing the startup, reset, and wake-up timings are calculated using the following formula: where and are found in table 7-44 . is the delay relative to rcsys, is the period of the cpu cl ock. if another cloc k source than rcsys is selected as cpu clock the startup time of the oscillator, , must be a dded to the wake- up time in the stop, deepstop, and static sleep modes. please refe r to the source for the cpu clock in the ?oscillator characteristics? on page 57 for more details about oscillator startup times. tt const n cpu t cpu + = t const n cpu t const t cpu t oscstart table 7-44. maximum reset and wake-up timing parameter measuring max (in s) max startup time from power-up, using regulator vddin_5 rising (10 mv/ms) time from v vddin_5 =0 to the first instruction entering the decode stage of cpu. vddcore is supplied by the internal regulator. 2600 0 startup time from reset release time from releasing a reset source (except por, bod18, and bod33) to the first instruction entering the decode stage of cpu. 1240 0 wake-up idle from wake-up event to the first instruction entering the decode stage of the cpu. 019 frozen 268 209 standby 268 209 stop 268+ 212 deepstop 268+ 212 static 268+ 212 t const n cpu t oscstart t oscstart t oscstart 71 32117ds?avr-01/12 at32uc3c figure 7-5. startup and reset time 7.9.2 reset_n characteristics internal reset decoding stage startup time from reset release reset time vddin_5, vddin_33 vddcore bod18 threshold at power-up voltage time bod33 threshold at power-up table 7-45. reset_n clock waveform parameters symbol parameter condition min. typ. max. units t reset reset_n minimum pulse length 2 * t rcsys clock cycles 72 32117ds?avr-01/12 at32uc3c 7.9.3 usart in spi mode timing 7.9.3.1 master mode figure 7-6. usart in spi master mode with (cpol= cpha= 0) or (cpol= cpha= 1) figure 7-7. usart in spi master mode with (cpol= 0 and cpha= 1) or (cpol= 1 and cpha= 0) note: 1. these values are based on simulation and characterization of other avr microcontrollers manufactured in the same pro- cess technology. these values are not covered by test limits in production. 2. where: uspi0 uspi1 miso spck mosi uspi2 uspi3 uspi4 miso spck mosi uspi5 table 7-46. usart in spi mode timing, master mode (1) symbol parameter conditions min max units uspi0 miso setup time before spck rises external capacitor = 40pf 26+ t sample (2) ns uspi1 miso hold time after spck rises 0 ns uspi2 spck rising to mosi delay 11 ns uspi3 miso setup time be fore spck falls 26+ t sample (2) ns uspi4 miso hold time after spck falls 0 ns uspi5 spck falling to mosi delay 11.5 ns t sample t spck t spck 2 t clkusart ------------------------------------ 1 2 -- - ?? ?? t clkusart ? = 73 32117ds?avr-01/12 at32uc3c maximum spi frequency, master output the maximum spi master output frequenc y is given by the following formula: where is the mosi delay, uspi2 or uspi5 depending on cpol and ncpha. is the maximum frequency of the spi pins. please refe r to the i/o pin characteristics section for the maximum frequency of the pins. is the maximum frequency of the clk_spi. refer to the spi chapter for a description of this clock. maximum spi frequency, master input the maximum spi master input frequenc y is given by the following formula: where is the miso setup and hold time, uspi0 + uspi1 or uspi3 + uspi4 depending on cpol and ncpha. is the spi slave response time. please refer to the spi slave datasheet for . is the maximum frequency of the clk_spi. refer to the spi chapter for a description of this clock. 7.9.3.2 slave mode figure 7-8. usart in spi slave mode with (cpol= 0 and cpha= 1) or (cpol= 1 and cpha= 0) f spckmax min f pinmax 1 spin ------------ f clkspi 2 9 ---------------------------- - , (, ) = spin f pinmax f clkspi f spckmax min 1 spin t valid + ----------------------------------- - f clkspi 2 9 ---------------------------- - (,) = spin t valid t valid f clkspi uspi7 uspi8 miso spck mosi uspi6 74 32117ds?avr-01/12 at32uc3c figure 7-9. usart in spi slave mode with (cpol= cpha= 0) or (cpol= cpha= 1) figure 7-10. usart in spi slave mode npcs timing note: 1. these values are based on simulation and characterization of other avr microcontrollers manufactured in the same pro- cess technology. these values are not covered by test limits in production. 2. where: uspi10 uspi11 miso spck mosi uspi9 uspi14 uspi12 uspi15 uspi13 nss spck, cpol=0 spck, cpol=1 table 7-47. usart in spi mode timing, slave mode (1) symbol parameter conditions min max units uspi6 spck falling to miso delay external capacitor = 40pf 27 ns uspi7 mosi setup time before spck rises t sample (2) + t clk_usart ns uspi8 mosi hold time after spck rises 0 ns uspi9 spck rising to miso delay 28 ns uspi10 mosi setup time before spck falls t sample (2) + t clk_usart ns uspi11 mosi hold time after spck falls 0 ns uspi12 nss setup time before spck rises 33 ns uspi13 nss hold time after spck falls 0 ns uspi14 nss setup time before spck falls 33 ns uspi15 nss hold time after spck rises 0 ns t sample t spck t spck 2 t clkusart ------------------------------------ 1 2 -- - + ?? ?? t clkusart ? = 75 32117ds?avr-01/12 at32uc3c maximum spi frequency, slave input mode the maximum spi slave input frequency is given by the following formula: where is the mosi setup and hold time, uspi7 + uspi8 or uspi10 + uspi11 depending on cpol and ncpha. is the maximum frequency of the clk_spi. refer to the spi chapter for a description of this clock. maximum spi frequency, slave output mode the maximum spi slave output frequency is given by the following formula: where is the miso delay, uspi6 or uspi9 depending on cpol and ncpha. is the spi master setup time. please refer to the spi masterdatasheet for . is the maximum frequency of the clk_spi. refer to the spi chapter for a description of this clock. is the maximum frequency of the spi pins. please refer to the i/o pin characteris- tics section for the maximum frequency of the pins. 7.9.4 spi timing 7.9.4.1 master mode figure 7-11. spi master mode with (cpol= nc pha= 0) or (cpol= ncpha= 1) f spckmax min f clkspi 2 9 ---------------------------- - 1 spin ------------ (,) = spin f clkspi f spckmax min f clkspi 2 9 ---------------------------- - f pinmax , 1 spin t setup + ------------------------------------ (,) = spin t setup t setup f clkspi f pinmax spi0 spi1 miso spck mosi spi2 76 32117ds?avr-01/12 at32uc3c figure 7-12. spi master mode with (cpol= 0 and ncpha= 1) or (cpol= 1 and ncpha= 0) note: 1. these values are based on simulation and characterization of other avr microcontrollers manufactured in the same pro- cess technology. these values are not covered by test limits in production. maximum spi frequency, master output the maximum spi master output frequenc y is given by the following formula: where is the mosi delay, spi2 or spi5 depending on cpol and ncpha. is the maximum frequency of the spi pins. please refer to the i/o pin characteristics section for the maximum frequency of the pins. maximum spi frequency, master input the maximum spi master input frequenc y is given by the following formula: where is the miso setup and hold time, spi0 + spi1 or spi3 + spi4 depending on cpol and ncpha. is the spi slave response time. please refer to the spi slave datasheet for . spi3 spi4 miso spck mosi spi5 table 7-48. spi timing, master mode (1) symbol parameter conditions min max units spi0 miso setup time before spck rises external capacitor = 40pf 28.5+ (t clk_spi )/2 ns spi1 miso hold time after spck rises 0 ns spi2 spck rising to mosi delay 10.5 ns spi3 miso setup time befo re spck falls 28.5 + (t clk_spi )/2 ns spi4 miso hold time after spck falls 0 ns spi5 spck falling to mosi delay 10.5 ns f spckmax min f pinmax 1 spin ------------ (,) = spin f pinmax f spckmax 1 spin t valid + ----------------------------------- - = spin t valid t valid 77 32117ds?avr-01/12 at32uc3c 7.9.4.2 slave mode figure 7-13. spi slave mode with (cpol= 0 and nc pha= 1) or (cpol= 1 and ncpha= 0) figure 7-14. spi slave mode with (cpol= ncp ha= 0) or (cpol= ncpha= 1) figure 7-15. spi slave mode npcs timing spi7 spi8 miso spck mosi spi6 spi10 spi11 miso spck mosi spi9 spi14 spi12 spi15 spi13 npcs spck, cpol=0 spck, cpol=1 78 32117ds?avr-01/12 at32uc3c note: 1. these values are based on simulation and characterization of other avr microcontrollers manufactured in the same pro- cess technology. these values are not covered by test limits in production. maximum spi frequency, slave input mode the maximum spi slave input frequency is given by the following formula: where is the mosi setup and hold time, spi7 + spi8 or spi10 + spi11 depending on cpol and ncpha. is the maximum frequency of the clk_spi. refer to the spi chap- ter for a description of this clock. maximum spi frequency, slave output mode the maximum spi slave output frequency is given by the following formula: where is the miso delay, spi6 or spi9 depending on cpol and ncpha. is the spi master setup time. please refer to the spi masterdatasheet for . is the maxi- mum frequency of the spi pins. please refer to the i/o pin characteristics section for the maximum frequency of the pins. 7.9.5 twim/twis timing figure 7-50 shows the twi-bus timing requirements and the compliance of the device with them. some of these requirements (t r and t f ) are met by the device wi thout requiring user inter- vention. compliance with the other requirements (t hd-sta , t su-sta , t su-sto , t hd-dat , t su-dat-i2c , t low- i2c , t high , and f twck ) requires user intervention through a ppropriate programming of the relevant table 7-49. spi timing, slave mode (1) symbol parameter conditions min max units spi6 spck falling to miso delay external capacitor = 40pf 29 ns spi7 mosi setup time before spck rises 0 ns spi8 mosi hold time after spck rises 6.5 ns spi9 spck rising to miso delay 30 ns spi10 mosi setup time before spck falls 0 ns spi11 mosi hold time after spck falls 5 ns spi12 npcs setup time before spck rises 0 ns spi13 npcs hold time after spck falls 1.5 ns spi14 npcs setup time before spck falls 0 ns spi15 npcs hold time after spck rises 1.5 ns f spckmax min f clkspi 1 spin ------------ (,) = spin f clkspi f spckmax min f pinmax 1 spin t setup + ------------------------------------ (, ) = spin t setup t setup f pinmax 79 32117ds?avr-01/12 at32uc3c twim and twis user interface registers. please refer to the twim and twis sections for more information . notes: 1. standard mode: ; fast mode: . 2. a device must internally provide a hold time of at least 300 ns for twd with reference to the falling edge of twck. notations: c b = total capacitance of one bus line in pf t clkpb = period of twi peripheral bus clock t prescaled = period of twi internal prescaled clock (see chapters on twim and twis) the maximum t hd;dat has only to be met if the device does not stretch the low period (t low-i2c ) of twck. table 7-50. twi-bus timing requirements symbol parameter mode minimum maximum unit requirement device requirement device t r twck and twd rise time standard (1) - 1000 ns fast (1) 20 + 0.1 c b 300 t f twck and twd fall time standard (1) -300 ns fast (1) 20 + 0.1 c b 300 t hd-sta (repeated) start hold time standard (1) 4.0 t clkpb - s fast (1) 0.6 t su-sta (repeated) start set-up time standard (1) 4.7 t clkpb - s fast (1) 0.6 t su-sto stop set-up time standard (1) 4.0 4t clkpb - s fast (1) 0.6 t hd-dat data hold time standard (1) 0.3 (2) 2t clkpb 3.45 ?? s fast (1) 0.9 t su-dat-i2c data set-up time standard (1) 250 2t clkpb -ns fast (1) 100 t su-dat --t clkpb -- t low-i2c twck low period standard (1) 4.7 4t clkpb - s fast (1) 1.3 t low --t clkpb -- t high twck high period standard (1) 4.0 8t clkpb - s fast (1) 0.6 f twck twck frequency standard (1) - 100 khz fast (1) 400 1 12t clkpb ----------------------- - f twck 100 khz f twck 100 khz > 80 32117ds?avr-01/12 at32uc3c 7.9.6 jtag timing figure 7-16. jtag interface signals note: 1. these values are based on simulation and characterization of other avr microcontrollers manufactured in the same pro- cess technology. these values are not covered by test limits in production. jtag2 jtag3 jtag1 jtag4 jtag0 tms/tdi tck tdo jtag5 jtag6 jtag7 jtag8 jtag9 jtag10 boundary scan inputs boundary scan outputs table 7-51. jtag timings (1) symbol parameter conditions min max units jtag0 tck low half-period external capacitor = 40pf 21.5 ns jtag1 tck high half-period 8.5 ns jtag2 tck period 29 ns jtag3 tdi, tms setup before tck high 6.5 ns jtag4 tdi, tms hold after tck high 0 ns jtag5 tdo hold time 12.5 ns jtag6 tck low to tdo valid 21.5 ns jtag7 boundary scan inputs setup time 0 ns jtag8 boundary scan inputs hold time 4.5 ns jtag9 boundary scan outputs hold time 11 ns jtag10 tck to boundary scan outputs valid 18 ns 81 32117ds?avr-01/12 at32uc3c 7.9.7 ebi timings see ebi i/o lines description for more details. note: 1. the maximum frequency of the smc interface is the same as the max frequency for the hsb. note: 1. these values are based on simulation and characterization of other avr microcontrollers manufactured in the same pro- cess technology. these values are not covered by test limits in production. 2. hold length = total cycle duration - setup duration - pulse durat ion. ?hold length? is for ?ncs rd hold length? or ?nrd hold length?. table 7-52. smc clock signal. symbol parameter max (1) units 1/(t cpsmc ) smc controller clock frequency f cpu mhz table 7-53. smc read signals with hold settings (1) symbol parameter conditions min units nrd controlled (read_mode = 1) smc 1 data setup before nrd high v vdd = 3.0v, drive strength of the pads set to the lowest, external capacitor = 40pf 32.5 ns smc 2 data hold after nrd high 0 smc 3 nrd high to nbs0/a0 change (2) nrd hold length * t cpsmc - 1.5 smc 4 nrd high to nbs1 change (2) nrd hold length * t cpsmc - 0 smc 5 nrd high to nbs2/a1 change (2) nrd hold length * t cpsmc - 0 smc 7 nrd high to a2 - a25 change (2) nrd hold length * t cpsmc - 5.6 smc 8 nrd high to ncs inactive (2) (nrd hold length - n cs rd hold length) * t cpsmc - 1.3 smc 9 nrd pulse width nrd pulse length * t cpsmc - 0.6 nrd controlled (read_mode = 0) smc 10 data setup before ncs high v vdd = 3.0v, drive strength of the pads set to the lowest, external capacitor = 40pf 34.1 ns smc 11 data hold after ncs high 0 smc 12 ncs high to nbs0/a0 change (2) ncs rd hold length * t cpsmc - 3 smc 13 ncs high to nbs0/a0 change (2) ncs rd hold length * t cpsmc - 2 smc 14 ncs high to nbs2/a1 change (2) ncs rd hold length * t cpsmc - 1.1 smc 16 ncs high to a2 - a25 change (2) ncs rd hold length * t cpsmc - 7.2 smc 17 ncs high to nrd inactive (2) (ncs rd hold length - nrd hold length) * t cpsmc - 2.2 smc 18 ncs pulse width ncs rd pulse length * t cpsmc - 3 82 32117ds?avr-01/12 at32uc3c note: 1. these values are based on simulation and characterization of other avr microcontrollers manufactured in the same pro- cess technology. these values are not covered by test limits in production. note: 1. these values are based on simulation and characterization of other avr microcontrollers manufactured in the same pro- cess technology. these values are not covered by test limits in production. 2. hold length = total cycle duration - setup duration - pulse duration. ?hold length? is for ?ncs wr hold length? or ?nwe hold length? table 7-54. smc read signals with no hold settings (1) symbol parameter conditions min units nrd controlled (read_mode = 1) smc 19 data setup before nrd high v vdd = 3.0v, drive strength of the pads set to the lowest, external capacitor = 40pf 32.5 ns smc 20 data hold after nrd high 0 nrd controlled (read_mode = 0) smc 21 data setup before ncs high v vdd = 3.0v, drive strength of the pads set to the lowest, external capacitor = 40pf 28.5 ns smc 22 data hold after ncs high 0 table 7-55. smc write signals with hold settings (1) symbol parameter conditions min units nrd controlled (read_mode = 1) smc 23 data out valid before nwe high v vdd = 3.0v, drive strength of the pads set to the lowest, external capacitor = 40pf (nwe pulse length - 1) * t cpsmc - 1.4 ns smc 24 data out valid after nwe high (2) nwe pulse length * t cpsmc - 4.7 smc 25 nwe high to nbs0/a0 change (2) nwe pulse length * t cpsmc - 2.7 smc 29 nwe high to nbs2/a1 change (2) nwe pulse length * t cpsmc - 0.7 smc 31 nwe high to a2 - a25 change (2) nwe pulse length * t cpsmc - 6.8 smc 32 nwe high to ncs inactive (2) (nwe hold pulse - ncs wr hold length) * t cpsmc - 2.5 smc 33 nwe pulse width nwe pulse length * t cpsmc - 0.2 nrd controlled (read_mode = 0) smc 34 data out valid before ncs high v vdd = 3.0v, drive strength of the pads set to the lowest, external capacitor = 40pf (ncs wr pulse length - 1) * t cpsmc - 2.2 ns smc 35 data out valid after ncs high (2) ncs wr hold length * t cpsmc - 5.1 smc 36 ncs high to nwe inactive (2) (ncs wr hold length - nwe hold length) * t cpsmc - 2 83 32117ds?avr-01/12 at32uc3c note: 1. these values are based on simulation and characterization of other avr microcontrollers manufactured in the same pro- cess technology. these values are not covered by test limits in production. figure 7-17. smc signals for ncs controlled accesses table 7-56. smc write signals with no hold settings (nwe controlled only) (1) symbol parameter conditions min units smc 37 nwe rising to a2-a25 valid v vdd = 3.0v, drive strength of the pads set to the lowest, external capacitor = 40pf 8.7 ns smc 38 nwe rising to nbs0/a0 valid 7.6 smc 40 nwe rising to a1/nbs2 change 8.7 smc 42 nwe rising to ncs rising 8.4 smc 43 data out valid before nwe rising (nwe pulse length - 1) * t cpsmc - 1.2 smc 44 data out valid after nwe rising 8.4 smc 45 nwe pulse width nwe pulse length * t cpsmc - 0 nrd ncs d0 - d15 nwe a2-a25 a0/a1/nbs[3:0] smc34 smc35 smc10 smc11 smc16 smc15 smc22 smc21 smc17 smc18 smc14 smc13 smc12 smc18 smc17 smc16 smc15 smc14 smc13 smc12 smc18 smc36 smc16 smc15 smc14 smc13 smc12 84 32117ds?avr-01/12 at32uc3c figure 7-18. smc signals for nrd and nrw controlled accesses (1) note: 1. these values are based on simulation and characterization of other avr microcontrollers manufactured in the same pro- cess technology. these values are not covered by test limits in production. 7.9.8 sdram signals note: 1. the maximum frequency of the sdramc interface is the same as the max frequency for the hsb. nrd ncs d0 - d15 nwe a2-a25 a0/a1/nbs[3:0] smc7 smc19 smc20 smc43 smc37 smc42 smc8 smc1 smc2 smc23 smc24 smc32 smc7 smc8 smc6 smc5 smc4 smc3 smc9 smc41 smc40 smc39 smc38 smc45 smc9 smc6 smc5 smc4 smc3 smc33 smc30 smc29 smc26 smc25 smc31 smc44 table 7-57. sdram clock signal symbol parameter max (1) units 1/(t cpsdck ) sdram controller clock frequency f cpu mhz 85 32117ds?avr-01/12 at32uc3c note: 1. these values are based on simulation and characterization of other avr microcontrollers manufactured in the same pro- cess technology. these values are not covered by test limits in production. table 7-58. sdram signal (1) symbol parameter conditions min units sdramc 1 sdcke high before sdck rising edge v vdd = 3.0v, drive strength of the pads set to the highest, external capacitor = 40pf on sdram pins except 8 pf on sdck pins 5.6 ns sdramc 2 sdcke low after sdck rising edge 7.3 sdramc 3 sdcke low before sdck rising edge 6.8 sdramc 4 sdcke high after sdck rising edge 8.3 sdramc 5 sdcs low before sdck rising edge 6.1 sdramc 6 sdcs high after sdck rising edge 8.4 sdramc 7 ras low before sdck rising edge 7 sdramc 8 ras high after sdck rising edge 7.7 sdramc 9 sda10 change before sdck rising edge 6.4 sdramc 10 sda10 change after sdck rising edge 7.1 sdramc 11 address change before sdck rising edge 4.7 sdramc 12 address change after sdck rising edge 4.4 sdramc 13 bank change before sdck rising edge 6.2 sdramc 14 bank change after sdck rising edge 6.9 sdramc 15 cas low before sdck rising edge 6.6 sdramc 16 cas high after sdck rising edge 7.8 sdramc 17 dqm change before sdck rising edge 6 sdramc 18 dqm change after sdck rising edge 6.7 sdramc 19 d0-d15 in setup before sdck rising edge 6.4 sdramc 20 d0-d15 in hold after sdck rising edge 0 sdramc 23 sdwe low before sdck rising edge 7 sdramc 24 sdwe high after sdck rising edge 7.4 sdramc 25 d0-d15 out valid before sdck rising edge 5.2 sdramc 26 d0-d15 out valid after sdck rising edge 5.6 86 32117ds?avr-01/12 at32uc3c figure 7-19. sdramc signals relative to sdck. ras a0 - a9, a11 - a13 d0 - d15 read sdck sda10 d0 - d15 to write sdramc 1 sdcke sdramc 2 sdramc 3 sdramc 4 sdcs sdramc 5 sdramc 6 sdramc 5 sdramc 6 sdramc 5 sdramc 6 sdramc 7 sdramc 8 cas sdramc 15 sdramc 16 sdramc 15 sdramc 16 sdwe sdramc 23 sdramc 24 sdramc 9 sdramc 10 sdramc 9 sdramc 10 sdramc 9 sdramc 10 sdramc 11 sdramc 12 sdramc 11 sdramc 12 sdramc 11 sdramc 12 ba0/ba1 sdramc 13 sdramc 14 sdramc 13 sdramc 14 sdramc 13 sdramc 14 sdramc 17 sdramc 18 sdramc 17 sdramc 18 dqm0 - dqm3 sdramc 19 sdramc 20 sdramc 25 sdramc 26 87 32117ds?avr-01/12 at32uc3c 7.9.9 macb characteristics note: 1. these values are based on simulation and characterization of other avr microcontrollers manufactured in the same pro- cess technology. these values are not covered by test limits in production. note: 1. these values are based on simulation and characterization of other avr microcontrollers manufactured in the same pro- cess technology. these values are not covered by test limits in production. table 7-59. ethernet mac signals (1) symbol parameter conditions min. max. unit mac 1 setup for mdio from mdc rising v vdd = 3.0v, drive strength of the pads set to the highest, external capacitor = 10pf on macb pins 02.5ns mac 2 hold for mdio from mdc rising 0 0.7 ns mac 3 mdio toggling from mdc falling 0 1.1 ns table 7-60. ethernet mac mii specific signals (1) symbol parameter conditions min. max. unit mac 4 setup for col from tx_clk rising v vdd = 3.0v, drive strength of the pads set to the highest, external capacitor = 10pf on macb pins 0ns mac 5 hold for col from tx_clk rising 0 ns mac 6 setup for crs from tx_clk rising 0.5 ns mac 7 hold for crs from tx_clk rising 0.5 ns mac 8 tx_er toggling from tx_clk rising 16.4 18.6 ns mac 9 tx_en toggling from tx_clk rising 14.5 15.3 ns mac 10 txd toggling from tx_clk rising 13.9 18.2 ns mac 11 setup for rxd from rx_clk 1.3 ns mac 12 hold for rxd from rx_clk 1.8 ns mac 13 setup for rx_er from rx_clk 3.4 ns mac 14 hold for rx_er from rx_clk 0 ns mac 15 setup for rx_dv from rx_clk 0.7 ns mac 16 hold for rx_dv from rx_clk 1.3n ns 88 32117ds?avr-01/12 at32uc3c figure 7-20. ethernet mac mii mode mac 4 mac 2 mac 5 mac 1 mdio mdc col mac 3 tx_clk mac 6 mac 7 crs tx_er mac 8 mac 9 tx_en mac 10 txd[3:0] rx_clk mac 11 mac 12 rxd[3:0] mac 13 mac 14 mac 15 mac 16 rx_er rx_dv 89 32117ds?avr-01/12 at32uc3c note: 1. these values are based on simulation and characterization of other avr microcontrollers manufactured in the same pro- cess technology. these values are not covered by test limits in production. figure 7-21. ethernet mac rmii mode table 7-61. ethernet mac rmii specific signals (1) symbol parameter conditions min. max. unit mac 21 tx_en toggling from tx_clk rising v vdd = 3.0v, drive strength of the pads set to the highest, external capacitor = 10pf on macb pins 11.7 12.5 ns mac 22 txd toggling from tx_clk rising 11.7 12.5 ns mac 23 setup for rxd from tx_clk 4.5 ns mac 24 hold for rxd from tx_clk 0 ns mac 25 setup for rx_er from tx_clk 3.4 ns mac 26 hold for rx_er from tx_clk 0 ns mac 27 setup for rx_dv from tx_clk 4.4 ns mac 28 hold for rx_dv from tx_clk 0 ns tx_clk tx_en mac 22 txd[1:0] rxd[3:0] mac 25 mac 26 mac 27 mac 28 rx_er rx_dv mac 21 mac 23 mac 24 90 32117ds?avr-01/12 at32uc3c 8. mechanical characteristics 8.1 thermal considerations 8.1.1 thermal data table 8-1 summarizes the thermal resistance data depending on the package. 8.1.2 junction temperature the average chip-junction temperature, t j , in c can be obtained from the following: 1. 2. where: ? ja = package thermal resistance, junction-to-ambient (c/w), provided in table 8-1 on page 90 . ? jc = package thermal resistance, junction-to-ca se thermal resistance (c/w), provided in table 8-1 on page 90 . ? heat sink = cooling device thermal resistance (c/w), provided in the device datasheet. ?p d = device power consumption (w) estimated from data provided in the section ?power consumption? on page 51 . ?t a = ambient temperature (c). from the first equation, the user can derive the estimated lifetime of the chip and decide if a cooling device is necessary or not. if a coolin g device is to be fitted on the chip, the second equation should be used to compute the resulting average chip-junction temperature t j in c. table 8-1. thermal resistance data symbol parameter condition package typ unit ja junction-to-ambient thermal resistance no air flow qfn64 20.0 c/w jc junction-to-case thermal resistance qfn64 0.8 ja junction-to-ambient thermal resistance no air flow tqfp64 40.5 c/w jc junction-to-case thermal resistance tqfp64 8.7 ja junction-to-ambient thermal resistance no air flow tqfp100 39.3 c/w jc junction-to-case thermal resistance tqfp100 8.5 ja junction-to-ambient thermal resistance no air flow lqfp144 38.1 c/w jc junction-to-case thermal resistance lqfp144 8.4 t j t a p d ja () + = t j t a p ( d ( heatsink jc )) ++ = 91 32117ds?avr-01/12 at32uc3c 8.2 package drawings figure 8-1. qfn-64 package drawing note: the exposed pad is not connected to anything internally, but should be soldered to ground to increase board level reliabil ity. table 8-2. device and package maximum weight 200 mg table 8-3. package characteristics moisture sensitivity level jdec j-std0-20d - msl 3 table 8-4. package reference jedec drawing reference ms-026 jesd97 classification e3 92 32117ds?avr-01/12 at32uc3c figure 8-2. tqfp-64 package drawing table 8-5. device and package maximum weight 300 mg table 8-6. package characteristics moisture sensitivity level jdec j-std0-20d - msl 3 table 8-7. package reference jedec drawing reference ms-026 jesd97 classification e3 93 32117ds?avr-01/12 at32uc3c figure 8-3. tqfp-100 package drawing table 8-8. device and package maximum weight 500 mg table 8-9. package characteristics moisture sensitivity level jdec j-std0-20d - msl 3 table 8-10. package reference jedec drawing reference ms-026 jesd97 classification e3 94 32117ds?avr-01/12 at32uc3c figure 8-4. lqfp-144 package drawing table 8-11. device and package maximum weight 1300 mg table 8-12. package characteristics moisture sensitivity level jdec j-std0-20d - msl 3 table 8-13. package reference jedec drawing reference ms-026 jesd97 classification e3 95 32117ds?avr-01/12 at32uc3c 8.3 soldering profile table 8-14 gives the recommended soldering profile from j-std-20. note: it is recommended to apply a soldering temperature higher than 250c. a maximum of three reflow passes is allowed per component. table 8-14. soldering profile profile feature green package average ramp-up rate (217c to peak) 3c/sec preheat temperature 175c 25c min. 150 c, max. 200 c temperature maintained above 217c 60-150 sec time within 5 ? c of actual peak temperature 30 sec peak temperature range 260 c ramp-down rate 6 c/sec time 25 ? c to peak temperature max. 8 minutes 96 32117ds?avr-01/12 at32uc3c 9. ordering information table 9-1. ordering information device ordering code carrier type package temperature operating range at32uc3c0512c at32uc3c0512c-alut tray lqfp 144 industrial (-40c to 85c) at32uc3c0512c-alur tape & reel at32uc3c0256c at32uc3c0256c-alut tray at32uc3c0256c-alur tape & reel at32uc3c0128c at32uc3c0128c-alut tray at32uc3c0128c-alur tape & reel at32uc3c064c at32uc3c064c-alut tray at32uc3c064c-alur tape & reel at32uc3c1512c at32uc3c1512c-aut tray tqfp 100 at32uc3c1512c-aur tape & reel at32uc3c1256c at32uc3c1256c-aut tray at32uc3c1256c-aur tape & reel AT32UC3C1128C AT32UC3C1128C-aut tray AT32UC3C1128C-aur tape & reel at32uc3c164c at32uc3c164c-aut tray at32uc3c164c-aur tape & reel at32uc3c2512c at32uc3c2512c-a2ut tray tqfp 64 at32uc3c2512c-a2ur tape & reel at32uc3c2512c-z2ut tray qfn 64 at32uc3c2512c-z2ur tape & reel at32uc3c2256c at32uc3c2256c-a2ut tray tqfp 64 at32uc3c2256c-a2ur tape & reel at32uc3c2256c-z2ut tray qfn 64 at32uc3c2256c-z2ur tape & reel at32uc3c2128c at32uc3c2128c-a2ut tray tqfp 64 at32uc3c2128c-a2ur tape & reel at32uc3c2128c-z2ut tray qfn 64 at32uc3c2128c-z2ur tape & reel at32uc3c264c at32uc3c264c-a2ut tray tqfp 64 at32uc3c264c-a2ur tape & reel at32uc3c264c-z2ut tray qfn 64 at32uc3c264c-z2ur tape & reel 97 32117ds?avr-01/12 at32uc3c 10. errata 10.1 rev e 10.1.1 adcifa 1 adcrefp/adcrefn can not be selected as an external adc refere nce by setting the adcifa.cfg.exref bit to one fix/workaround a voltage reference can be applied on adcrefp/adcrefn pins if the adcifa.cfg.exref bit is set to zero, the adcifa.cfg.rs bit is set to zero and the volt- age reference applied on a dcrefp/adcrefn pins is high er than the internal 1v reference. 10.1.2 ast 1 ast wake signal is released one ast clock cycle after the busy bit is cleared after writing to the status clear register (scr) the wake signal is released one ast clock cycle after the busy bit in the status register (sr.busy) is cleared. if entering sleep mode directly after the busy bit is cleared the part will wake up immediately. fix/workaround read the wake enable register (wer) and write this value back to the same register. wait for busy to clear before entering sleep mode. 10.1.3 awire 1 awire memory_speed_request comm and does not return correct cv the awire memory_speed_request command does not retu rn a cv co rresponding to the formula in the awire debug interface chapter. fix/workaround issue a dummy read to address 0x100000000 before issuing the memory_speed_request command and use this formula instead: 10.1.4 power manager 1 twis may not wake the device from sleep mode if the cpu is put to a sleep mode (except idle and frozen) directly after a twi start condi- tion, the cpu may not wake upon a twis address match. the request is nacked. fix/workaround when using the twi address match to wake t he device from sleep, do not switch to sleep modes deeper than frozen. another solution is to enable asynchronous eic wake on the twis clock (twck) or twis data (twd) pi ns, in order to wake the system up on bus events. f sab 7 f aw cv 3 ? ---------------- - = 98 32117ds?avr-01/12 at32uc3c 10.1.5 scif 1 pllcount value larger than zero can cause pllen glitch initializing the pllcount with a value greater than zero creates a glitch on the pllen sig- nal during asynchronous wake up. fix/workaround the lock-masking mechanism for the pll should not be used. the pllcount field of the pll control register should always be written to zero. 2 pll lock might not clear after disable under certain circumstances, the lock signal from the phase locked loop (pll) oscillator may not go back to zero after th e pll oscillator has been disabl ed. this can cause the prop- agation of clock signals with the wrong frequency to parts of the system that use the pll clock. fix/workaround pll must be turned off befor e entering stop, deepstop or static sleep modes. if pll has been turned off, a delay of 30us must be observed after the pll has been enabled again before the scif.pll0lock bit can be used as a valid indication that the pll is locked. 3 bod33 reset locks the device if bod33 is enabled as a reset source (scif.bod33.ctrl=0x1 ) and when vddin_33 power supply voltage falls below the bod33 voltage (sci f.bod33.level), the device is locked permanently under reset even if the power supply goes back above bod33 reset level. in order to unlock the device, an external reset event should be applied on reset_n. fix/workaround use an external bod on vddin_33 or an external reset source. 10.1.6 spi 1 spi data transfer hangs with csr0.csaat==1 and mr.modfdis==0 when csr0.csaat==1 and mode fault detection is enabled (mr.modfdis==0), the spi module will not start a data transfer. fix/workaround disable mode fault detection by writing a one to mr.modfdis. 2 disabling spi has no effect on the sr.tdre bit disabling spi has no effect on the sr.tdre bit whereas the write data command is filtered when spi is disabled. writing to tdr when spi is disabled will not clear sr.tdre. if spi is disabled during a pdca transfer, the pdca will continue to write data to tdr until its buffer is empty, and this data will be lost. fix/workaround disable the pdca, add two nops, and disable the spi. to continue the transfer, enable the spi and pdca. 3 spi disable does not work in slave mode spi disable does not work in slave mode. fix/workaround read the last received data, then perform a software reset by writing a one to the software reset bit in the control register (cr.swrst). 99 32117ds?avr-01/12 at32uc3c 4 spi bad serial clock generation on 2nd chip_select when scbr=1, cpol=1, and ncpha=0 when multiple chip selects (cs) are in use, if one of the baudrates equal 1 while one (csrn.scbr=1) of the others do not equal 1, and csrn.cpol=1 and csrn.ncpha=0, then an additional pulse will be genera ted on sck. fix/workaround when multiple cs are in use, if one of the baudrates equals 1, the others must also equal 1 if csrn.cpol=1 and csrn.ncpha=0. 10.1.7 tc 1 channel chaining skips first pulse for upper channel when chaining two channels using the block mode register, the first pulse of the clock between the channels is skipped. fix/workaround configure the lower channel with ra = 0x1 and rc = 0x2 to produce a dummy clock cycle for the upper channel. after the dummy cycle has been generated, indicated by the sr.cpcs bit, reconfigure the ra and rc registers for the lower channel with the real values. 10.1.8 twim 1 smbalert bit may be set after reset for twim0 and twim1 modules, the smbus alert (smbalert) bit in the status register (sr) might be erroneously set after system reset. fix/workaround after system reset, clear the sr.smbalert bit before commencing any twi transfer. for twim2 module, the smbus alert (smbalert) is not implemented but the bit in the sta- tus register (sr) is erroneously set once twim2 is enabled. fix/workaround none. 10.1.9 twis 1 clearing the nak bit before the btf bit is set locks up the twi bus when the twis is in transmit mode, clearing the nak received (nak) bit of the status reg- ister (sr) before the end of the acknowl edge/not acknowledge cycle will cause the twis to attempt to continue transmitting data, thus locking up the bus. fix/workaround clear sr.nak only after the byte transfer finished (btf) bit of the same register has been set. 10.1.10 usbc 1 upinrqx.inrq field is limited to 8-bits in host mode, when using the upinrqx.inrq feature together with the multi-packet mode to launch a finite number of packet among multi-packet, the multi-packet size (located in the descriptor table) is limited to the upinrq x.inrq value multiply by the pipe size. fix/workaround upinrqx.inrq value shall be less than the number of configured multi-packet. 2 in usb host mode, downstream resume feature does not work (uhcon.resume=1). 100 32117ds?avr-01/12 at32uc3c fix/workaround none. 3 in host mode, the disconnection during out transition is not supported in usb host mode, a pipe can not work if the previous usb device disconnection has occurred during a usb transfer. fix/workaround reset the usbc (usbcon.usb=0 and =1) after a device disconnection (uhint.ddisci). 4 in usb host mode, entering suspend mode can fail in usb host mode, entering suspend mode can fail when uhcon.sofe=0 is done just after a sof reception (uhint.hsofi). fix/workaround check that uhnum.flenhigh is below 185 in full speed and below 21 in low speed before clearing uhcon.sofe. 5 in usb host mode, entering suspend mode for low speed device can fail when the usb freeze (usbcon.frzclk=1) is done just after uhcon.sofe=0. fix/workaround when entering suspend mode (uhcon.sofe is cleared), check that usbfsm.drdstate is not equal to three before freezing the clock (usbcon.frzclk=1). 10.1.11 wdt 1 wdt control register does not have synchronization feedback when writing to the timeout pr escale select (psel), time ban prescale select (tban), enable (en), or wdt mode (mode) fieldss of the wdt control register (ctrl), a synchro- nizer is started to propagate the values to the wdt clcok domain. this synchronization takes a finite amount of time, but only the status of the synchronization of the en bit is reflected back to the user. writing to the synch ronized fields during synchronization can lead to undefined behavior. fix/workaround -when writing to the affected fields, the user must ensure a wait corresponding to 2 clock cycles of both the wdt peripheral bus clock and the selected wdt clock source. -when doing writes that changes the en bit, the en bit can be read back until it reflects the written value. 101 32117ds?avr-01/12 at32uc3c 10.2 rev d 10.2.1 adcifa 1 adcrefp/adcrefn can not be selected as an external adc refere nce by setting the adcifa.cfg.exref bit to one fix/workaround a voltage reference can be applied on adcrefp/adcrefn pins if the adcifa.cfg.exref bit is set to zero, the adcifa.cfg.rs bit is set to zero and the volt- age reference applied on a dcrefp/adcrefn pins is high er than the internal 1v reference. 10.2.2 ast 1 ast wake signal is released one ast clock cycle after the busy bit is cleared after writing to the status clear register (scr) the wake signal is released one ast clock cycle after the busy bit in the status register (sr.busy) is cleared. if entering sleep mode directly after the busy bit is cleared the part will wake up immediately. fix/workaround read the wake enable register (wer) and write this value back to the same register. wait for busy to clear before entering sleep mode. 10.2.3 awire 1 awire memory_speed_request comm and does not return correct cv the awire memory_speed_request command does not retu rn a cv co rresponding to the formula in the awire debug interface chapter. fix/workaround issue a dummy read to address 0x100000000 before issuing the memory_speed_request command and use this formula instead: 10.2.4 gpio 1 clearing interrupt flags can mask other interrupts when clearing interrupt flags in a gpio port, interrupts on other pins of that port, happening in the same clock cycle will not be registered. fix/workaround read the pvr register of the port before and af ter clearing the interrupt to see if any pin change has happened while clearing the interr upt. if any change occurred in the pvr between the reads, they must be treated as an interrupt. 10.2.5 power manager 1 clock failure detector (cfd) can be issued while turning off the cfd while turning off the cfd, the cfd bit in the status register (sr) can be set. this will change the main cl ock source to rcsys. fix/workaround solution 1: enable cfd in terrupt. if cfd interrupt is issues after turning off the cfd, switch back to original main clock source. solution 2: only turn off the cfd while running the main clock on rcsys. f sab 7 f aw cv 3 ? ---------------- - = 102 32117ds?avr-01/12 at32uc3c 2 requesting clocks in idle sleep modes will mask all other pb clocks than the requested in idle or frozen sl eep mode, all the pb clocks will be froz en if the twis or the ast need to wake the cpu up. fix/workaround disable the twis or the ast before entering idle or frozen sleep mode. 3 twis may not wake the device from sleep mode if the cpu is put to a sleep mode (except idle and frozen) directly after a twi start condi- tion, the cpu may not wake upon a twis address match. the request is nacked. fix/workaround when using the twi address match to wake t he device from sleep, do not switch to sleep modes deeper than frozen. another solution is to enable asynchronous eic wake on the twis clock (twck) or twis data (twd) pi ns, in order to wake the system up on bus events. 10.2.6 scif 1 pllcount value larger than zero can cause pllen glitch initializing the pllcount with a value greater than zero creates a glitch on the pllen sig- nal during asynchronous wake up. fix/workaround the lock-masking mechanism for the pll should not be used. the pllcount field of the pll control register should always be written to zero. 2 pll lock might not clear after disable under certain circumstances, the lock signal from the phase locked loop (pll) oscillator may not go back to zero after th e pll oscillator has been disabl ed. this can cause the prop- agation of clock signals with the wrong frequency to parts of the system that use the pll clock. fix/workaround pll must be turned off befor e entering stop, deepstop or static sleep modes. if pll has been turned off, a delay of 30us must be observed after the pll has been enabled again before the scif.pll0lock bit can be used as a valid indication that the pll is locked. 3 bod33 reset locks the device if bod33 is enabled as a reset source (scif.bod33.ctrl=0x1 ) and when vddin_33 power supply voltage falls below the bod33 voltage (sci f.bod33.level), the device is locked permanently under reset even if the power supply goes back above bod33 reset level. in order to unlock the device, an external reset event should be applied on reset_n. fix/workaround use an external bod on vddin_33 or an external reset source. 10.2.7 spi 1 spi data transfer hangs with csr0.csaat==1 and mr.modfdis==0 when csr0.csaat==1 and mode fault detection is enabled (mr.modfdis==0), the spi module will not start a data transfer. fix/workaround disable mode fault detection by writing a one to mr.modfdis. 103 32117ds?avr-01/12 at32uc3c 2 disabling spi has no effect on the sr.tdre bit disabling spi has no effect on the sr.tdre bit whereas the write data command is filtered when spi is disabled. writing to tdr when spi is disabled will not clear sr.tdre. if spi is disabled during a pdca transfer, the pdca will continue to write data to tdr until its buffer is empty, and this data will be lost. fix/workaround disable the pdca, add two nops, and disable the spi. to continue the transfer, enable the spi and pdca. 3 spi disable does not work in slave mode spi disable does not work in slave mode. fix/workaround read the last received data, then perform a software reset by writing a one to the software reset bit in the control register (cr.swrst). 4 spi bad serial clock generation on 2nd chip_select when scbr=1, cpol=1, and ncpha=0 when multiple chip selects (cs) are in use, if one of the baudrates equal 1 while one (csrn.scbr=1) of the others do not equal 1, and csrn.cpol=1 and csrn.ncpha=0, then an additional pulse will be genera ted on sck. fix/workaround when multiple cs are in use, if one of the baudrates equals 1, the others must also equal 1 if csrn.cpol=1 and csrn.ncpha=0. 10.2.8 tc 1 channel chaining skips first pulse for upper channel when chaining two channels using the block mode register, the first pulse of the clock between the channels is skipped. fix/workaround configure the lower channel with ra = 0x1 and rc = 0x2 to produce a dummy clock cycle for the upper channel. after the dummy cycle has been generated, indicated by the sr.cpcs bit, reconfigure the ra and rc registers for the lower channel with the real values. 10.2.9 twim 1 smbalert bit may be set after reset for twim0 and twim1 modules, the smbus alert (smbalert) bit in the status register (sr) might be erroneously set after system reset. fix/workaround after system reset, clear the sr.smbalert bit before commencing any twi transfer. for twim2 module, the smbus alert (smbalert) is not implemented but the bit in the sta- tus register (sr) is erroneously set once twim2 is enabled. fix/workaround none. 2 twim twalm polarity is wrong the twalm signal in the twim is active high instead of active low. fix/workaround use an external inverter to invert the signal going into the twim. when using both twim and twis on the same pins, the twalm cannot be used. 104 32117ds?avr-01/12 at32uc3c 10.2.10 twis 1 clearing the nak bit before the btf bit is set locks up the twi bus when the twis is in transmit mode, clearing the nak received (nak) bit of the status reg- ister (sr) before the end of the acknowl edge/not acknowledge cycle will cause the twis to attempt to continue transmitting data, thus locking up the bus. fix/workaround clear sr.nak only after the byte transfer finished (btf) bit of the same register has been set. 2 twis stretch on address match error when the twis stretches twck due to a slave address match, it also holds twd low for the same duration if it is to be receiving data. when twis releases twck, it releases twd at the same time. this can cause a twi timing violation. fix/workaround none. 3 twalm forced to gnd the twalm pin is forced to gnd when the alternate function is selected and the twis module is enabled. fix/workaround none. 10.2.11 usbc 1 upinrqx.inrq field is limited to 8-bits in host mode, when using the upinrqx.inrq feature together with the multi-packet mode to launch a finite number of packet among multi-packet, the multi-packet size (located in the descriptor table) is limited to the upinrq x.inrq value multiply by the pipe size. fix/workaround upinrqx.inrq value shall be less than the number of configured multi-packet. 2 in usb host mode, downstream resume feature does not work (uhcon.resume=1). fix/workaround none. 3 in host mode, the disconnection during out transition is not supported in usb host mode, a pipe can not work if the previous usb device disconnection has occurred during a usb transfer. fix/workaround reset the usbc (usbcon.usb=0 and =1) after a device disconnection (uhint.ddisci). 4 in usb host mode, entering suspend mode can fail in usb host mode, entering suspend mode can fail when uhcon.sofe=0 is done just after a sof reception (uhint.hsofi). fix/workaround check that uhnum.flenhigh is below 185 in full speed and below 21 in low speed before clearing uhcon.sofe. 5 in usb host mode, entering suspend mode for low speed device can fail when the usb freeze (usbcon.frzclk=1) is done just after uhcon.sofe=0. fix/workaround when entering suspend mode (uhcon.sofe is cleared), check that usbfsm.drdstate is not equal to three before freezing the clock (usbcon.frzclk=1). 105 32117ds?avr-01/12 at32uc3c 10.2.12 wdt 1 clearing the watchdog timer (wdt) counter in second half of timeout period will issue a watchdog reset if the wdt counter is cleared in the second half of the ti meout period, the wdt will immedi- ately issue a watchdog reset. fix/workaround use twice as long timeout period as needed and clear the wdt counter within the first half of the timeout period. if the wdt counter is cl eared after the first half of the timeout period, you will get a watchdog reset immediately. if the wdt counter is not clea red at all, the time before the reset will be tw ice as long as needed. 2 wdt control register does not have synchronization feedback when writing to the timeout pr escale select (psel), time ban prescale select (tban), enable (en), or wdt mode (mode) fieldss of the wdt control register (ctrl), a synchro- nizer is started to propagate the values to the wdt clcok domain. this synchronization takes a finite amount of time, but only the status of the synchronization of the en bit is reflected back to the user. writing to the synch ronized fields during synchronization can lead to undefined behavior. fix/workaround -when writing to the affected fields, the user must ensure a wait corresponding to 2 clock cycles of both the wdt peripheral bus clock and the selected wdt clock source. -when doing writes that changes the en bit, the en bit can be read back until it reflects the written value. 106 32117ds?avr-01/12 at32uc3c 11. datasheet revision history please note that the referring page numbers in th is section are referred to this document. the referring revision in this section are referring to the document revision. 11.1 rev. d ? 01/12 11.2 rev. c ? 08/11 11.3 rev. b ? 03/11 1 errata: updated 2 pm: clock mask table updated 3 fixed pllopt field description in scif chapter 4 mdma: swapped bit descriptions for ier and idr 5 macb: usrio register description and bit descriptions for imr/idr/ier updated 6 usbc: upcon.pfreeze and upinrqn description updated 7acifa: updated 8 adcifa: cfg.muxset, ssmq description and conversion result s section updated 9 dacifb: calibration section updated 10 electrical characteristics: adcrefp/adcrefn added 1 electrical characteristics updated: - i/o pins characteristics - 8mhz/1mhz rc oscillator (rc8m) characteristics - 1.8v voltage regulator characteristics - 3.3v voltage regulator characteristics - 1.8vbrown out detector (bod18) characteristics - 3.3vbrown out detector (bod33) characteristics - 5vbrown out detector (bod50) characteristics - analog to digital converter (adc) and sample and hold (s/dh) characteristics - analog comparator characteristics 2 errata: updated 3twis: updated 1 package and pinout: added supply column. updated peripheral functions 2 supply and startup considerations: updated i/o lines power 3 pm: added awen description 4 scif: added vregcr register 107 32117ds?avr-01/12 at32uc3c 11.4 rev. a ? 10/10 5 ast: updated digital tuner formula 6 sdramc: cleaned-up sdcs/ncs names. added version register 7 sau: updated sr.idle 8 usart: updated 9 canif: updated address map figure 10 usbc: updated 11 dacifb: updated 12 programming and debugging: added jtag data registers section 13 electrical characteristics: updated 14 ordering information: updated 15 errata: updated 1 initial revision 108 32117ds?avr-01/12 at32uc3c table of contents 1 description ............ .............. .............. ............... .............. .............. ............ 3 2 overview ............ ................ ................ ............... .............. .............. ............ 5 2.1 block diagram ....................................................................................................5 2.2 configuration summary .....................................................................................6 3 package and pinout ................. ................ ................. ................ ............... 8 3.1 package .............................................................................................................8 3.2 peripheral multiplexing on i/o lines .................................................................11 3.3 signals description ..........................................................................................18 3.4 i/o line considerations ...................................................................................24 4 processor and architecture .... ................ ................. ................ ............. 25 4.1 features ..........................................................................................................25 4.2 avr32 architecture .........................................................................................25 4.3 the avr32uc cpu ........................................................................................26 4.4 programming model ........................................................................................30 4.5 exceptions and interrupts ................................................................................34 5 memories ............... .............. .............. ............... .............. .............. .......... 39 5.1 embedded memories ......................................................................................39 5.2 physical memory map .....................................................................................40 5.3 peripheral address map ..................................................................................41 5.4 cpu local bus mapping .................................................................................43 6 supply and startup c onsiderations ............ ................. .............. .......... 46 6.1 supply considerations .....................................................................................46 6.2 startup considerations ....................................................................................49 7 electrical characteristics ... .............. ............... .............. .............. .......... 50 7.1 absolute maximum ratings* ...........................................................................50 7.2 supply characteristics .....................................................................................50 7.3 maximum clock frequencies ..........................................................................51 7.4 power consumption ........................................................................................51 7.5 i/o pin characteristics .....................................................................................55 7.6 oscillator characteristics .................................................................................57 7.7 flash characteristics .......................................................................................60 7.8 analog characteristics .....................................................................................61 109 32117ds?avr-01/12 at32uc3c 7.9 timing characteristics .....................................................................................70 8 mechanical characteristics ....... ................. ................ ................. .......... 90 8.1 thermal considerations ..................................................................................90 8.2 package drawings ...........................................................................................91 8.3 soldering profile ..............................................................................................95 9 ordering information .......... .............. ............... .............. .............. .......... 96 10 errata ............. ................ ................. ................ ................. .............. .......... 97 10.1 rev e ................................................................................................................97 10.2 rev d ..............................................................................................................101 11 datasheet revision history .. ................ ................. ................ ............. 106 11.1 rev. d ? 01/12 ...............................................................................................106 11.2 rev. c ? 08/11 ...............................................................................................106 11.3 rev. b ? 03/11 ...............................................................................................106 11.4 rev. a ? 10/10 ...............................................................................................107 32117ds-avr?01/12 ? 2012 atmel corporation. all rights reserved. atmel ? , atmel logo and combinations thereof, avr ? and others are registered trademarks or trademarks of atmel corporation or its subsidiaries. other terms and product names may be trademarks of others. headquarters international atmel corporation 2325 orchard parkway san jose, ca 95131 usa tel: 1(408) 441-0311 fax: 1(408) 487-2600 atmel asia unit 1-5 & 16, 19/f bea tower, millennium city 5 418 kwun tong road kwun tong, kowloon hong kong tel: (852) 2245-6100 fax: (852) 2722-1369 atmel europe le krebs 8, rue jean-pierre timbaud bp 309 78054 saint-quentin-en- yvelines cedex france tel: (33) 1-30-60-70-00 fax: (33) 1-30-60-71-11 atmel japan 9f, tonetsu shinkawa bldg. 1-24-8 shinkawa chuo-ku, tokyo 104-0033 japan tel: (81) 3-3523-3551 fax: (81) 3-3523-7581 product contact web site www.atmel.com technical support avr32@atmel.com sales contact www.atmel.com/contacts literature requests www.atmel.com/literature 107486 disclaimer: the information in this document is provided in connection with atmel products. no license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of atmel products. except as set forth in atmel?s terms and condi- tions of sale located on atmel?s web site, atmel assumes no li ability whatsoever and disclaims any express, implied or statutor y warranty relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particu lar purpose, or non-infringement. in no event shall atmel be liable for any direct, indirect, consequential, punitive, special or i nciden- tal damages (including, without limitation, damages for loss of profits, business interruption, or loss of information) arising out of the use or inability to use this document, even if atme l has been advised of the possibility of such damages. atmel makes no representations or warranties with respect to the accuracy or comp leteness of the contents of this document and reserves the rig ht to make changes to specifications and product descriptions at any time without notice. atmel does not make any commitment to update the information contained her ein. unless specifically provided otherwise, atmel products are not suitable for, and shall not be used in, automotive applications. atmel?s products are not int ended, authorized, or warranted for use as components in applications in tended to support or sustain life. |
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